IP Library › Granted Patent US 11,763,896
Granted Patent B2
US 11,763,896 · App. 17/951,593 · Granted Sep 19, 2023

Preread and read threshold voltage optimization

Inventors: Seungjune Jeon (Santa Clara, CA); Zhenming Zhou (San Jose, CA); Zhenlei Shen (Milpitas, CA)
Assignee: Micron Technology, Inc.
G11C16/34G06F9/30101G11C16/10G11C16/26G11C29/42
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,763,896
App. No.
17/951,593
Granted
Sep 19, 2023
Kind
B2
Abstract

A request to read data at the memory device is received. A first read operation is performed to read the data at the memory device using a first read threshold voltage. The data read at the memory device using the first read threshold voltage is determined to be associated with a first unsuccessful correction of an error. Responsive to determining that the data read at the memory device using the first read threshold voltage is associated with the first unsuccessful correction of the error, a second read threshold voltage is stored at a register to replace a preread threshold voltage previously stored at the register that is associated with the memory device. The first preread threshold voltage was previously used to perform a preread operation at the memory device. A second read operation to read the data at the memory device is performed using the second read threshold voltage.

Claims (52)

1. A system comprising:

a memory device; and

a processing device, operatively coupled to the memory device, to:

receive a request to perform a write operation to write first data to the memory device;

perform a first preread operation to read second data at the memory device using a first preread threshold voltage;

responsive to determining that the second data is associated with a first unsuccessful error correction operation, store a second preread threshold voltage at a register to replace the first preread threshold voltage previously stored at the register;

perform a second preread operation to read the second data at the memory device using the second preread threshold voltage; and

perform, based on the second preread operation, a write operation that writes a subset of the first data to the memory device.

2. The system of claim 1 , wherein performing the first preread operation further comprises:

determining data values of a first subset of the second data that match data values of a first subset of third data, and data values of a second subset of the second data that differ from data values of a second subset of the third data.

3. The system of claim 2 , wherein performing the write operation further comprises:

maintaining the data values of the first subset of the second data that match the data values of the first subset of the third data.

4. The system of claim 1 , wherein the first preread threshold voltage is greater than the second preread threshold voltage.

5. The system of claim 1 , wherein the processing device is further to:

pre-load the first preread threshold voltage to the register.

6. The system of claim 1 , wherein the register is an on-die register associated with a die of the memory device.

7. The system of claim 1 , wherein the processing device is further to:

receive a request to read data at the memory device;

perform a first read operation to read the data at the memory device using a first read threshold voltage.

8. A method comprising:

receiving, by a processing device, a request to perform a write operation to write first data to a memory device;

performing a first preread operation to read second data at the memory device using a first preread threshold voltage;

responsive to determining that the second data is associated with a first unsuccessful error correction operation, storing a second preread threshold voltage at a register to replace the first preread threshold voltage previously stored at the register;

performing a second preread operation to read the second data at the memory device using the second preread threshold voltage; and

performing, based on the second preread operation, a write operation that writes a subset of the first data to the memory device.

9. The method of claim 8 , wherein performing the first preread operation further comprises:

determining data values of a first subset of the second data that match data values of a first subset of third data, and data values of a second subset of the second data that differ from data values of a second subset of the third data.

10. The method of claim 9 , wherein performing the write operation further comprises:

maintaining the data values of the first subset of the second data that match the data values of the first subset of the third data.

11. The method of claim 8 , wherein the first preread threshold voltage is greater than the second preread threshold voltage.

12. The method of claim 8 , further comprising:

pre-loading the first preread threshold voltage to the register.

13. The method of claim 8 , wherein the register is an on-die register associated with a die of the memory device.

14. The method of claim 8 , further comprising:

receiving a request to read data at the memory device;

performing a first read operation to read the data at the memory device using a first read threshold voltage.

15. A non-transitory computer-readable storage medium comprising executable instructions that, when executed by a processing device, cause the processing device to:

receive a request to perform a write operation to write first data to a memory device;

perform a first preread operation to read second data at the memory device using a first preread threshold voltage;

responsive to determining that the second data is associated with a first unsuccessful error correction operation, store a second preread threshold voltage at a register to replace the first preread threshold voltage previously stored at the register;

perform a second preread operation to read the second data at the memory device using the second preread threshold voltage; and

perform, based on the second preread operation, a write operation that writes a subset of the first data to the memory device.

16. The non-transitory computer-readable storage medium of claim 15 , wherein performing the first preread operation further comprises:

determining data values of a first subset of the second data that match data values of a first subset of third data, and data values of a second subset of the second data that differ from data values of a second subset of the third data.

17. The non-transitory computer-readable storage medium of claim 16 , wherein performing the write operation further comprises:

maintaining the data values of the first subset of the second data that match the data values of the first subset of the third data.

18. The non-transitory computer-readable storage medium of claim 15 , wherein the first preread threshold voltage is greater than the second preread threshold voltage.

19. The non-transitory computer-readable storage medium of claim 15 , further comprising executable instructions that, when executed by the processing device, cause the processing device to:

pre-load the first preread threshold voltage to the register.

20. The non-transitory computer-readable storage medium of claim 15 , further comprising executable instructions that, when executed by the processing device, cause the processing device to:

receive a request to read data at the memory device;

perform a first read operation to read the data at the memory device using a first read threshold voltage.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 23, 2022
From: JEON, SEUNGJUNE; ZHOU, ZHENMING; SHEN, ZHENLEI
To: MICRON TECHNOLOGY, INC.
Reel/Frame 061195/0814 →
Continuity (3)
Continuation 17171486 · Feb 9, 2021
Continuation 16715639 · Dec 16, 2019
Related Publication 20230017981A1 · Jan 19, 2023