Methods of manufacturing semiconductor devices

1. A method of manufacturing a semiconductor device, the method comprising:

forming line patterns on a substrate;

conformally forming a first protecting spacer layer on the substrate having the line patterns;

forming sacrificial spacers on sidewalls of the line patterns, the first protecting spacer layer being between each of the sacrificial spacers and a corresponding one of the line patterns;

conformally forming a second protecting spacer layer on the substrate, after forming the sacrificial spacers, each of the first and second protecting spacer layers being formed of an insulating material having an etch selectivity with respect to the sacrificial spacers;

forming a contact hole between the line patterns, each of the sacrificial spacers being between the contact hole and a corresponding one of the line patterns, respectively;

forming a contact plug in the contact hole; and

removing the sacrificial spacers to form air gaps,

wherein forming the contact hole includes:

forming a filling line pattern between the line patterns, the filling line pattern being formed after forming the second protecting spacer layer;

forming capping mask patterns defining line type openings crossing the line patterns and the filling line pattern;

removing portions of the filling line pattern exposed by the line type openings to form fence concave regions and a filling pillar pattern under each of the capping mask patterns;

forming insulating fences filling the fence concave regions, respectively; and

removing the capping mask patterns and the filling pillar patterns.

2. The method of claim 1 , wherein:

the capping mask patterns are formed of a material having an etch selectivity with respect to the filling line pattern and the insulating fences; and

the insulating fences are formed of a material having an etch selectivity with respect to the filling line pattern.

3. The method of claim 2 , wherein:

the filling line pattern is formed of silicon oxide;

the insulating fences are formed of silicon nitride; and

the capping mask pattern is formed of poly-crystalline silicon.

4. The method of claim 2 , wherein forming the insulating fences includes:

forming a fence insulating layer filling the fence concave regions on the substrate; and

planarizing the fence insulating layer until the capping mask patterns are exposed.

5. The method of claim 1 , wherein at least portions of the second protecting spacer layer and the sacrificial spacers under the line type openings are recessed when the fence concave regions are formed.

6. The method of claim 5 , wherein the recessed sacrificial spacers under the line type openings have a predetermined height after the fence concave regions are formed.

7. The method of claim 5 , wherein, when the fence concave regions are formed, the sacrificial spacers under the line type openings are etched until the first protecting spacer layer thereunder is exposed, so that portions of the sacrificial spacers respectively disposed under the capping mask patterns are completely separated from each other.

8. The method of claim 1 , wherein forming the air gaps, the contact hole, and the contact plug includes:

anisotropically etching the second and first protecting spacer layers under the filling pillar patterns to form the contact hole after removing the filling pillar patterns, wherein top ends of the sacrificial spacers between the insulating fences are exposed;

forming a lower plug filling a lower region of the contact hole;

removing the exposed sacrificial spacers to form the air gaps;

forming a capping spacer closing top ends of the air gaps in the contact hole; and

forming an upper plug filling an upper region of the contact hole.

9. The method of claim 8 , wherein forming the capping spacer includes:

forming a first sub-spacer layer on the substrate having the air gaps and the lower plug;

forming a second sub-spacer layer on the first sub-spacer layer; and

performing an etch-back process on the second sub-spacer layer and the first sub-spacer layer,

wherein a step coverage property of the first sub-spacer layer is poorer than a step coverage property of the second sub-spacer layer.