Systems and methods for distributing programming speed among blocks with different program-erase cycle counts
Non-volatile memory systems and method for managing P/E cycling is disclosed. Memory systems include multi-plane (e.g., 2-plane or 4-plane) programming operations in which new blocks within a plane replace faulty/bad blocks. Existing blocks, having undergone several P/E cycles more than the new block(s), require a lower programming voltage and are programmed using an adaptive (reduced) programming voltage. New block(s) require an additional voltage, and a delta voltage is added to the programming voltage to increase the gate-to-channel voltage. To prevent the delta voltage from over-programming the existing blocks, a voltage equal to the delta voltage is applied bit lines of the existing blocks, thereby reducing the effective gate-to-channel voltage on the existing blocks. In this manner, the same programming voltage is applied to planes in a multi-plane programming operation, and the existing blocks receive a relatively lower gate-to-channel voltage, while the new block(s) receive a relatively higher gate-to-channel voltage.
1. A method for performing a programming operation in a multi-plane programming system, the method comprising:
receiving, at a first word line of a first block, a voltage equal to a programming voltage plus a delta voltage, wherein the first block is located in a first plane and has undergone a first number of program-erase cycles, and
receiving, at a second word line of a second block, the voltage, wherein the second block is located in a second plane and has undergone a second number of program-erase cycles, wherein the second number of program-erase cycles is less than the first number of program-erase cycles; and
receiving, at a first bit line, the delta voltage, wherein the first bit line crosses the first word line, and wherein the delta voltage is based upon the first number of program-erase cycles.
2. The method according to claim 1 , further comprising receiving, at a second bit line, zero voltage, wherein the second bit line crosses the second word line.
3. The method according to claim 2 , wherein:
a first memory cell is provided where the first word line and the first bit line cross,
a second memory cell is provided where the second word line and the second bit line cross, and
based upon the delta voltage applied to the first bit line, a gate-to-channel voltage at the second memory cell is higher than that at the first memory cell.
4. The method according to claim 1 , wherein the delta voltage is directly proportional to the first number of program-erase cycles.
5. The method according to claim 1 , wherein:
a first page located in the first block receives a first effective voltage based on the voltage, and
a second page located in the second block receives a second effective voltage that is greater than the first effective voltage.
6. The method according to claim 5 , further comprising:
receiving, at a third word line of a third block and a fourth word line of a fourth block, the voltage, wherein:
the third block is located in a third plane and has undergone a third number of program-erase cycles, and
the fourth block is located in a fourth plane and has undergone a fourth number of program-erase cycles, and
the second number of program-erase cycles is less than i) the third number of program-erase cycles and ii) the fourth number of program-erase cycles.
7. A memory system for performing a programming operation in a multi-plane programming system, the memory system comprising:
a memory controller configured to cause a shared programming voltage line to:
receive, at a first word line of a first block, a voltage equal to a programming voltage plus a positive delta voltage, wherein the first block is located in a first plane and has undergone a first number of program-erase cycles;
receive, at a second word line of a second block, the voltage, wherein the second block is located in a second plane and has undergone a second number of program-erase cycles, wherein the second number of program-erase cycles is less than the first number of program-erase cycles; and
receive, at a first bit line, the positive delta voltage, wherein the first bit line crosses the first word line.
8. The memory system according to claim 7 , wherein the memory controller is further configured to cause the shared programming voltage line to receive, at a second bit line, zero voltage, wherein the second bit line crosses the second word line.
9. The memory system according to claim 8 , wherein:
a first memory cell is provided where the first word line and the first bit line cross,
a second memory cell is provided where the second word line and the second bit line cross, and
based upon the delta voltage applied to the first bit line, a gate-to-channel voltage at the second memory cell is higher than that at the first memory cell.
10. The memory system according to claim 7 , wherein the positive delta voltage is based upon the first number of program-erase cycles.
11. The memory system according to claim 10 , wherein the positive delta voltage is directly proportional to the first number of program-erase cycles.
12. The memory system according to claim 7 , wherein:
a first page located on the first block receives a first effective voltage based on the voltage, and
a second page located in the second block receives a second effective voltage that is greater than the first effective voltage.
13. The memory system according to claim 12 , wherein the memory controller is further configured to:
receive, at a third word line of a third block and a fourth word line of a fourth block, the voltage, wherein:
the third block is located in a third plane and has undergone a third number of program-erase cycles, and
the fourth block is located in a fourth plane and has undergone a fourth number of program-erase cycles, and
the second number of program-erase cycles is less than i) the third number of program-erase cycles and ii) the fourth number of program-erase cycles.
14. A non-volatile memory system, comprising:
a first block and a second block;
a memory controller configured to:
apply, at a first word line of the first block, a voltage equal to a programming voltage plus a delta voltage, wherein the first block is located in a first plane and has undergone a first number of program-erase cycles;
apply, at a second word line of the second block, the voltage, wherein the second block is located in a second plane and has undergone a second number of program-erase cycles, wherein the second number of program-erase cycles is less than the first number of program-erase cycles; and
apply, at a first bit line, the delta voltage, wherein the first bit line crosses the first word line, and wherein the delta voltage is based on the first number of program-erase cycles.
15. The non-volatile memory system according to claim 14 , wherein the memory controller is further configured to cause a shared programming voltage line to receive, at the second bit line, zero voltage, wherein the second bit line crosses the second word line.
16. The non-volatile memory system according to claim 15 , wherein:
a first memory cell is provided where the first word line and the first bit line cross,
a second memory cell is provided where the second word line and the second bit line cross, and
based upon the delta voltage applied to the first bit line, a gate-to-channel voltage at the second memory cell is higher than that at the first memory cell.
17. The non-volatile memory system according to claim 14 , wherein:
a first page located in the first block receives a first effective voltage based on the voltage, and
a second page located in the second block receives a second effective voltage that is greater than the first effective voltage.
18. The non-volatile memory system according to claim 17 , wherein the memory controller is further configured to cause a shared programming voltage line to:
receive, at a third word line of a third block and a fourth word line of a fourth block, the voltage, wherein:
the third block is located in a third plane and has undergone a third number of program-erase cycles, and
the fourth block is located in a fourth plane and has undergone a fourth number of program-erase cycles, and
the second number of program-erase cycles is less than i) the third number of program-erase cycles and ii) the fourth number of program-erase cycles.