IP Library Granted Patent US 11,784,052
Granted Patent B2
US 11,784,052 · App. 17/094,241 · Granted Oct 10, 2023

Dipole-engineered high-k gate dielectric and method forming same

Inventors: Te-Yang Lai (Hsinchu, TW); Chun-Yen Peng (Hsinchu, TW); Sai-Hooi Yeong (Zhubei, TW); Chi On Chui (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H01L21/28185H01L21/3115H01L21/823462H01L27/0886H01L29/513H01L21/823431
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Quick Facts
Patent No.
US 11,784,052
App. No.
17/094,241
Granted
Oct 10, 2023
Kind
B2
Abstract

A method includes forming an oxide layer on a semiconductor region, and depositing a first high-k dielectric layer over the oxide layer. The first high-k dielectric layer is formed of a first high-k dielectric material. The method further includes depositing a second high-k dielectric layer over the first high-k dielectric layer, wherein the second high-k dielectric layer is formed of a second high-k dielectric material different from the first high-k dielectric material, depositing a dipole film over and contacting a layer selected from the first high-k dielectric layer and the second high-k dielectric layer, performing an annealing process to drive-in a dipole dopant in the dipole film into the layer, removing the dipole film, and forming a gate electrode over the second high-k dielectric layer.

Claims (57)

1. A method comprising:

forming a first oxide layer on a first semiconductor region;

depositing a first high-k dielectric layer over the first oxide layer, wherein the first high-k dielectric layer is formed of a first high-k dielectric material;

depositing a first dipole film, wherein the first dipole film is over and in contact with the first high-k dielectric layer;

performing a first annealing process to drive-in a first dipole dopant in the first dipole film into the first high-k dielectric layer;

removing the first dipole film;

depositing a second high-k dielectric layer over the first high-k dielectric layer; and

forming a first gate electrode over the second high-k dielectric layer.

2. The method of claim 1 , wherein the second high-k dielectric layer has a higher k value than the first high-k dielectric layer.

3. The method of claim 1 , wherein the second high-k dielectric layer has a lower k value than the first high-k dielectric layer.

4. The method of claim 1 further comprising:

forming a second oxide layer on a second semiconductor region, wherein both of the first high-k dielectric layer and the second high-k dielectric layer further extend on the second oxide layer;

depositing a second dipole film over and contacting the second high-k dielectric layer, wherein the second dipole film overlaps the second semiconductor region;

performing a second annealing process to drive-in a second dipole dopant in the second dipole film into the second high-k dielectric layer;

removing the second dipole film; and

forming a second gate electrode over the second high-k dielectric layer, wherein the second gate electrode overlaps the second semiconductor region.

5. The method of claim 4 further comprising, before the second annealing process, removing the second dipole film from a region directly over the first semiconductor region.

6. The method of claim 1 , wherein the first dipole film comprises a material selected from lanthanum oxide, lanthanum nitride, aluminum oxide, or combinations thereof.

7. A method comprising:

forming a first oxide layer on a first semiconductor region;

depositing a first high-k dielectric layer comprising a first high-k dielectric material;

depositing a second high-k dielectric layer comprising a second high-k dielectric material different from the first high-k dielectric material, wherein the second high-k dielectric layer is overlying and contacts the first high-k dielectric layer;

driving a first dipole dopant into the first high-k dielectric layer and the second high-k dielectric layer, so that a first peak concentration of the first dipole dopant is at a first top surface of the first high-k dielectric layer or a second top surface of the second high-k dielectric layer;

after the first dipole dopant is driven, forming a gate electrode over the second high-k dielectric layer; and

forming a source/drain region on a side of the gate electrode.

8. The method of claim 7 , wherein the driving the first dipole dopant comprises:

depositing a lanthanum-comprising dipole film over and contacting one of the first high-k dielectric layer and the second high-k dielectric layer; and

performing an annealing process.

9. The method of claim 7 , wherein the driving the first dipole dopant comprises:

depositing an aluminum-comprising dipole film over and contacting one of the first high-k dielectric layer and the second high-k dielectric layer; and

performing an annealing process.

10. The method of claim 7 , wherein the first peak concentration of the first dipole dopant is at the first top surface, and the method further comprises diffusing a second dipole dopant different from the first dipole dopant, wherein the second dipole dopant has a second peak concentration at the second top surface.

11. The method of claim 10 , wherein a first one of the first dipole dopant and the second dipole dopant is lanthanum, and a second one of the first dipole dopant and the second dipole dopant is aluminum, and both of lanthanum and aluminum are diffused into each of the first high-k dielectric layer and the second high-k dielectric layer.

12. The method of claim 7 , wherein the second high-k dielectric layer has a lower k value than the first high-k dielectric layer.

13. A method comprising:

forming a first transistor comprising:

forming a first portion of a first high-k dielectric layer;

forming a first portion of a second high-k dielectric layer, wherein the second high-k dielectric layer is over the first high-k dielectric layer, and wherein the first high-k dielectric layer and the second high-k dielectric layer have different k values; and

driving a first dipole dopant into the first portion of the first high-k dielectric layer and the first portion of the second high-k dielectric layer, wherein the first dipole dopant has a first peak concentration at an interface between the first portion of the first high-k dielectric layer and the first portion of the second high-k dielectric layer; and

forming a second transistor comprising:

forming a second portion of the first high-k dielectric layer;

forming a second portion of the second high-k dielectric layer; and

driving a second dipole dopant into the second portion of the second high-k dielectric layer, wherein the second dipole dopant has a second peak concentration at a top surface of the second portion of the second high-k dielectric layer.

14. The method of claim 13 , wherein the driving the first dipole dopant comprises:

before forming the second high-k dielectric layer, depositing a dipole film over and contacting the first portion of the first high-k dielectric layer; and

performing an annealing process.

15. The method of claim 13 , wherein the driving the second dipole dopant comprises:

depositing a dipole film over and contacting the second portion of the second high-k dielectric layer; and

performing an annealing process.

16. The method of claim 13 , wherein the first dipole dopant and the second dipole dopant are selected from lanthanum and aluminum.

17. The method of claim 16 , wherein a first one of the first dipole dopant and the second dipole dopant is lanthanum, and a second one of the first dipole dopant and the second dipole dopant is aluminum.

18. The method of claim 17 , wherein the first transistor and the second transistor are of a same conductivity type.

19. The method of claim 1 , wherein the second high-k dielectric layer is deposited at a time after the first dipole film is removed.

20. The method of claim 1 further comprising:

depositing a second dipole film, wherein the first dipole film is over and in contact with the second high-k dielectric layer;

performing a second annealing process to drive-in a second dipole dopant in the second dipole film into the second high-k dielectric layer; and

after the second annealing process, removing the second dipole film.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 11, 2020
From: LAI, TE-YANG; PENG, CHUN-YEN; YEONG, SAI-HOOI; CHUI, CHI ON
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 054331/0076 →
Continuity (2)
Provisional Application 63031099 · May 28, 2020
Related Publication 20210375629A1 · Dec 2, 2021
Cited By (1)
US 12,727,231