Ferroelectric channel field effect transistor
Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a ferroelectric structure including a channel region and a source/drain region, a gate dielectric layer disposed over the channel region of the ferroelectric structure, a gate electrode disposed on the gate dielectric layer, and a source/drain contact disposed on the source/drain region of the ferroelectric structure. The ferroelectric structure includes gallium nitride, indium nitride, or indium gallium nitride. The ferroelectric structure is doped with a dopant.
1. A semiconductor device, comprising:
a first gate electrode;
a first gate dielectric layer over the first gate electrode;
a ferroelectric structure disposed on the first gate dielectric layer and comprising a channel region and a source/drain region;
a second gate dielectric layer disposed over the channel region of the ferroelectric structure;
a second gate electrode disposed on the second gate dielectric layer; and
a source/drain contact disposed on the source/drain region of the ferroelectric structure,
wherein the ferroelectric structure comprises gallium nitride, indium nitride, or indium gallium nitride.
2. The semiconductor device of claim 1 , wherein the ferroelectric structure comprises a dopant.
3. The semiconductor device of claim 2 , wherein the dopant comprises scandium.
4. The semiconductor device of claim 1 , wherein the first gate dielectric layer and the second gate dielectric layer comprise hafnium oxide, silicon oxide, aluminum oxide, aluminum nitride.
5. The semiconductor device of claim 1 ,
wherein the first gate dielectric layer comprises a first thickness,
wherein the second gate dielectric layer comprises a second thickness smaller than the first thickness.
6. The semiconductor device of claim 5 ,
Wherein the first thickness is between about 4 nm and about 20 nm,
Wherein the second thickness is between about 1 nm and about 2 nm.
7. The semiconductor device of claim 1 , wherein the first gat electrode and the second gate electrode comprise tungsten, nickel, tantalum, titanium, aluminum, copper, cobalt, tantalum nitride, titanium nitride, or ruthenium.
8. The semiconductor device of claim 1 , the first gate dielectric layer does not extend directly below the source/drain contact.
9. The semiconductor device of claim 1 , wherein the ferroelectric structure is crystalline.
10. A semiconductor structure, comprising:
a substrate;
a channel layer disposed on the substrate and comprising a first source/drain region, a second source/drain region, and a channel region between the first source/drain region and the second source/drain region;
a gate dielectric layer over the channel region;
a first source/drain contact over the first source/drain region; and
a second source/drain contact over the second source/drain region,
wherein the channel layer comprises:
a bottom nitride layer on the substrate,
a ferroelectric semiconductor layer on the bottom nitride layer, and
a top nitride layer on the ferroelectric semiconductor layer.
11. The semiconductor structure of claim 10 , wherein the ferroelectric semiconductor layer comprises a wurtzite crystalline structure.
12. The semiconductor structure of claim 10 , wherein the ferroelectric semiconductor layer comprises scandium doped gallium nitride, scandium doped indium nitride, or scandium doped indium gallium nitride.
13. The semiconductor structure of claim 12 , wherein the bottom nitride layer and the top nitride layer comprise undoped gallium nitride or indium-doped gallium nitride.
14. The semiconductor structure of claim 12 , wherein the bottom nitride layer and the top nitride layer comprise aluminum nitride.
15. The semiconductor structure of claim 10 , wherein the gate dielectric layer comprises hafnium oxide, silicon oxide, aluminum oxide, aluminum nitride.
16. The semiconductor structure of claim 10 ,
wherein the ferroelectric semiconductor layer is crystalline,
wherein the ferroelectric semiconductor layer comprises a (0001) crystalline face facing upward.
17. A semiconductor device, comprising:
a substrate;
a ferroelectric semiconductor fin arising from the substrate and extending lengthwise along a first direction, the ferroelectric semiconductor fin comprising a first source/drain region, a second source/drain region, and channel region sandwiched between the first source/drain region and the second source/drain region along the first direction;
an isolation feature on the substrate and around a base portion of the ferroelectric semiconductor fin;
a first gate dielectric layer on a first sidewall of the ferroelectric semiconductor fin;
a first electrode adjacent the first gate dielectric layer such that the first gate dielectric layer is sandwiched between the ferroelectric semiconductor fin and the first electrode along a second direction perpendicular to the first direction;
a second gate dielectric layer on a second sidewall;
a second electrode adjacent the second gate dielectric layer such that the second gate dielectric layer is sandwiched between the ferroelectric semiconductor fin and the second electrode along the second direction;
a first source/drain contact disposed over the first source/drain region; and
a second source/drain contact disposed over the second source/drain region,
wherein the first gate dielectric layer, the first electrode, the second gate dielectric layer, and the second electrode are disposed on the isolation feature.
18. The semiconductor device of claim 17 , wherein the ferroelectric semiconductor fin comprises a III-V semiconductor material and a dopant.
19. The semiconductor device of claim 18 , wherein the III-V semiconductor material is selected from a group consisting of indium nitride, gallium nitride and indium gallium nitride.
20. The semiconductor device of claim 18 , wherein the dopant comprises scandium.