Ferroelectric channel field effect transistor
Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a ferroelectric structure including a channel region and a source/drain region, a gate dielectric layer disposed over the channel region of the ferroelectric structure, a gate electrode disposed on the gate dielectric layer, and a source/drain contact disposed on the source/drain region of the ferroelectric structure. The ferroelectric structure includes gallium nitride, indium nitride, or indium gallium nitride. The ferroelectric structure is doped with a dopant.
1. A semiconductor device, comprising:
a substrate;
a III-V compound semiconductor layer over the substrate and comprising a first source/drain region, a second source/drain region, and a channel region sandwiched between the first source/drain region and the second source/drain region;
a first source/drain contact disposed over and in contact with the first source/drain region;
a second source/drain contact disposed over and in contact with the second source/drain region;
a gate dielectric layer continuously disposed along a sidewall of the first source/drain contact, a top surface of the channel region, and a sidewall of the second source/drain contact; and
a gate electrode disposed over the gate dielectric layer and spaced apart from the sidewall of the first source/drain contact, the top surface of the channel region, and the sidewall of the second source/drain contact by the gate dielectric layer,
wherein the channel region is doped with a dopant to exhibit ferroelectric property,
wherein the first source/drain region and the second source/drain region are free of the dopant.
2. The semiconductor device of claim 1 , wherein the III-V compound semiconductor layer comprises gallium nitride, indium nitride, or indium gallium nitride.
3. The semiconductor device of claim 1 , wherein the dopant comprises scandium (Sc).
4. The semiconductor device of claim 1 , wherein the channel region comprises a wurtzite crystalline structure.
5. The semiconductor device of claim 4 , wherein a horizontal surface of the channel region comprises a (0001) crystalline face.
6. The semiconductor device of claim 1 , wherein the gate dielectric layer comprises hafnium oxide, silicon oxide, aluminum oxide, or aluminum nitride.
7. The semiconductor device of claim 1 , wherein the first source/drain contact and the second source/drain contact comprise tungsten, nickel, tantalum, titanium, aluminum, copper, cobalt, tantalum nitride, titanium nitride, or ruthenium.
8. A semiconductor device, comprising:
a ferroelectric structure comprising a first source/drain region, a second source/drain region, and a channel region sandwiched between the first source/drain region and the second source/drain region along a direction;
a front gate dielectric layer disposed over the channel region;
a front gate electrode disposed over the front gate dielectric layer;
a first source/drain contact over the first source/drain region;
a second source/drain contact over the second source/drain region;
a back gate dielectric layer disposed below and in contact with a bottom surface of the ferroelectric structure; and
a back gate electrode disposed below and in contact with a bottom surface of the back gate dielectric layer,
wherein the front gate dielectric layer comprises a first width along the direction and the back gate dielectric layer comprises a second width along the direction,
wherein the first width is greater than the second width.
9. The semiconductor device of claim 8 , wherein the back gate dielectric layer is disposed directly below the front gate dielectric layer.
10. The semiconductor device of claim 8 , wherein the back gate dielectric layer is off-centered such that a geometric center line of the front gate electrode is not aligned with a geometric center line of the back gate electrode.
11. The semiconductor device of claim 8 , wherein the ferroelectric structure comprises gallium nitride, indium nitride, or indium gallium nitride.
12. The semiconductor device of claim 11 , wherein the ferroelectric structure comprises scandium as a dopant.
13. The semiconductor device of claim 8 ,
wherein the front gate dielectric layer comprises a first thickness,
wherein the back gate dielectric layer comprises a second thickness greater than the first thickness.
14. The semiconductor device of claim 8 , wherein the front gate dielectric layer and the back gate dielectric layer comprise hafnium oxide, silicon oxide, aluminum oxide, aluminum nitride.
15. The semiconductor device of claim 8 , wherein, along the direction, the ferroelectric structure is sandwiched between two isolation structures.
16. The semiconductor device of claim 15 , wherein the two isolation structures comprise silicon oxide.
17. A semiconductor device, comprising:
a ferroelectric structure comprising a first source/drain region, a second source/drain region, and a channel region sandwiched between the first source/drain region and the second source/drain region along a direction;
a front gate dielectric layer disposed over the channel region;
a front gate electrode disposed over the front gate dielectric layer;
a first source/drain contact over the first source/drain region;
a second source/drain contact over the second source/drain region;
a back gate dielectric layer disposed below and in contact with a bottom surface of the ferroelectric structure; and
a back gate electrode disposed below and in contact with a bottom surface of the back gate dielectric layer,
wherein the ferroelectric structure comprises III-V semiconductor and a dopant,
wherein the front gate dielectric layer comprises a first thickness,
wherein the back gate dielectric layer comprises a second thickness greater than the first thickness.
18. The semiconductor device of claim 17 ,
wherein the III-V semiconductor comprise gallium nitride, indium nitride, or indium gallium nitride,
wherein the dopant comprises scandium (Sc).
19. The semiconductor device of claim 17 ,
wherein the front gate dielectric layer comprises a first width along the direction and the back gate dielectric layer comprises a second width along the direction,
wherein the first width is greater than the second width.
20. The semiconductor device of claim 19 , wherein the back gate dielectric layer is disposed directly below the front gate dielectric layer.