Semiconductor device

1. A system on chip (SoC) comprising:

a plurality of intellectual property (IP) blocks;

a clock management unit (CMU) configured to perform clock gating on at least one of the IP blocks, the at least one of the IP blocks is configured to provide a request signal to the CMU indicating the at least one of the IP blocks desires to enter a selected one of a sleep mode and an active mode; and

a power management unit (PMU) configured to control a power supply to the SoC;

wherein the PMU is configured to cut off the power supply to the SoC by turning off a power control circuit if none of the plurality of IP blocks provide the request signal to the CMU within a pre-defined period of time.

2. The SoC of claim 1 , wherein the CMU outputs an output clock signal and an acknowledgement signal (Ack) to the at least one of the IP blocks in response to the request signal indicating the at least one of the IP blocks desires to enter the active mode, and activates the Ack signal upon determining the output clock signal is stable.

3. The SoC of claim 2 , wherein the CMU deactivates the acknowledgement signal to indicate the CMU has stopped outputting the output clock signal in response to the request signal indicating the at least one of the IP blocks desires to enter the sleep mode, and then stops providing the output clock signal to the at least one of the IP blocks.

4. The SoC of claim 2 , wherein the CMU comprises a controller configured to receive a first signal from a crystal oscillator and a second signal from a phase locked loop (PLL), and configured to provide one of the received signals as the output clock signal and the acknowledgement signal in response to the request signal.

5. The SoC of claim 1 , wherein the CMU comprises:

a multiplexer configured to receive an internal clock signal and an external clock signal, and configured to provide one of the received clock signals as an output clock signal.

6. The SoC of claim 1 , wherein the CMU comprises:

a frequency dividing circuit configured to divide an input clock signal to generate a divided clock signal, and configured to provide the divided clock signal as an output clock signal.

7. The SoC of claim 1 , wherein the CMU comprises:

a shortstop circuit configured to perform an operation on an input clock signal to generate a resulting clock signal comprising a plurality of pulses during a first period and a constant level during a second period, and configured to provide the resulting clock signal as an output clock signal.

8. The SoC of claim 2 , wherein the CMU comprises: a control circuit configured to output a control signal and the acknowledgement signal in response to the request signal; and a clock source configured to output the output clock signal in response to the control signal.

9. The SoC of claim 1 , wherein the CMU comprises:

a first clock component configured to provide a first request signal indicating a first one of the IP blocks desires to enter one of a sleep mode and an active mode;

a second clock component configured to provide a second request signal indicating a second one of the IP blocks desires to enter one of a sleep mode and an active mode; and

a third clock component configured to start providing a clock signal to both the first and second clock components when one of the first and second request signals indicate a desire to enter the active mode, and stop providing the clock signal when both of the first and second request signals indicate a desire to enter the sleep mode.

10. The SoC of claim 2 , wherein the CMU comprises:

a clock component configured to perform the clock gating;

a channel management (CM) circuit configured to manage a channel connecting the CM circuit to the one IP block; and

a wire connecting the clock component to the CM circuit, wherein the request signal is sent across the wire from the CM circuit to the clock component, and wherein the Ack signal is sent across the wire from the clock component to the CM circuit.

11. A system on chip (SoC) comprising:

a plurality of intellectual property (IP) blocks;

a clock management unit (CMU) configured to perform clock gating on at least one of the IP blocks, one of the IP blocks providing a request signal to the CMU indicating that the one of the IP blocks desires to enter a selected one of a sleep mode and an active mode; and

a power management unit (PMU) configured to control a power supply to the SoC;

wherein the CMU comprises a plurality of clock components forming a parent-child relationship with each other, wherein a child clock component is configured to transmit a sub request signal to a parent clock component and the parent clock component is configured to transmit an acknowledgement signal to the child clock component; and

wherein the PMU is configured to cut off the power supply to the SoC if the plurality of clock components are disabled.

12. The SoC of claim 11 , wherein, in response to the request signal indicating that the one of the IP blocks desires to enter the sleep mode, the CMU is configured to disable a phase locked loop (PLL).

13. The SoC of claim 11 , wherein the CMU is configured to provide an acknowledgement signal to indicate that the CMU has stopped outputting an output clock signal in response to the request signal indicating that the one of the IP blocks desires to enter the sleep mode, and then stops providing the output clock signal to the one of the IP blocks.

14. The SoC of claim 11 , wherein the PMU is further configured to cut off the power supply to the SoC when no request signals have been sent by the IP blocks during a given period.

15. The SoC of claim 11 , wherein the CMU comprises a controller configured to receive a first signal from a crystal oscillator and a second signal from a phase locked loop (PLL), and configured to provide one of the received signals as an output clock signal and an acknowledgement signal in response to the request signal.

16. The SoC of claim 11 , wherein the CMU comprises:

a multiplexer configured to receive an internal clock signal and an external clock signal, and configured to provide one of the received clock signals as an output clock signal; and

a control circuit configured to provide an acknowledgement signal in response to the request signal.

17. The SoC of claim 11 , wherein the CMU comprises:

a frequency dividing circuit configured to divide an input clock signal to generate a divided clock signal, and configured to provide the divided clock signal as an output clock signal; and

a control circuit configured to provide an acknowledgement signal in response to the request signal.

18. The SoC of claim 11 , wherein the CMU comprises:

a shortstop circuit configured to perform an operation on an input clock signal to generate a resulting clock signal comprising a plurality of pulses during a first period and a constant level during a second period, and configured to provide the resulting clock signal as an output clock signal; and

a control circuit configured to provide an acknowledgement signal in response to the request signal.

19. The SoC of claim 11 , wherein the CMU comprises:

a control circuit configured to output a control signal and an acknowledgement signal in response to the request signal; and

a clock source configured to output a clock signal in response to the control signal.

20. The SoC of claim 11 , wherein the CMU comprises:

a first clock component configured to provide a first request signal indicating that a first one of the IP blocks desires to enter one of a sleep mode and an active mode;

a second clock component configured to provide a second request signal indicating that a second one of the IP blocks desires to enter one of a sleep mode and an active mode; and

a third clock component configured to start providing a clock signal to both the first and second clock components when one of the first and second request signals indicate a desire to enter the active mode, and stop providing the clock signal when both of the first and second request signals indicate a desire to enter the sleep mode.

21. The SoC of claim 11 , wherein the CMU comprises:

a clock component configured to perform the clock gating;

a channel management (CM) circuit configured to manage a channel connecting the CM circuit to the at least one of IP blocks; and

a wire connecting the clock component to the CM circuit, wherein the request signal is sent across the wire from the CM circuit to the clock component, and wherein an acknowledgement signal is sent across the wire from the clock component to the CM circuit.

22. A system on chip (SoC) comprising:

a plurality of intellectual property (IP) blocks;

a clock management unit (CMU) configured to perform clock gating on at least one of the plurality of IP blocks, the at least one of the plurality of IP blocks configured to provide a request signal to the CMU indicating the at least one of the plurality of IP blocks desires to enter a selected one of a sleep mode and an active mode; and

a power management unit (PMU) configured to control a power supply to the SoC;

wherein the PMU is configured to cut off the power supply to the SoC if the CMU receives at least one request signal indicating that the plurality of IP blocks desire to enter the sleep mode.

23. A system on chip (SoC) comprising:

a plurality of intellectual property (IP) blocks;

a clock management unit (CMU) configured to perform clock gating on at least one of the plurality of IP blocks, the at least one of the plurality of IP blocks configured to provide a request signal to the CMU indicating the at least one of the plurality of IP blocks desires to enter a selected one of a sleep mode and an active mode; and

a power management unit (PMU) configured to control a power supply to the SoC;

wherein a frequency of an output clock from the CMU decreases as the PMU performs a power-down sequence.

24. The SoC of claim 23 , wherein the power-down sequence cuts off the power supply to at least one of unused parts.