Control transfer termination instructions of an instruction set architecture (ISA)
In an embodiment, the present invention includes a processor having an execution logic to execute instructions and a control transfer termination (CTT) logic coupled to the execution logic. This logic is to cause a CTT fault to be raised if a target instruction of a control transfer instruction is not a CTT instruction. Other embodiments are described and claimed.
1. A processor comprising:
a storage to store state information;
first circuitry to decode instructions, including a first indirect control transfer instruction, a second indirect control transfer instruction of a different type than the first indirect control transfer instruction, and a control transfer termination instruction, wherein the control transfer termination instruction comprises an opcode and has a length of at least four bytes;
second circuitry coupled to the first circuitry and the storage to execute the first indirect control transfer instruction to
perform an indirect control transfer to a target instruction, wherein a two bit field having a first value is to be stored in the storage in response to the first indirect control transfer instruction, and wherein the first value of the two bit field is different than a second value of the two bit field to be stored in the storage in response to the second indirect control transfer instruction; and
third circuitry, responsive to the first indirect control transfer instruction, to:
determine whether the target instruction is a valid control transfer point for the first indirect control transfer instruction, wherein for the control transfer termination instruction to be the valid control transfer point for the first indirect control transfer instruction depends on a value of the two bit field;
in response to a determination the target instruction is not the valid control transfer point, cause a first exception to be raised; and
in response to a determination the target instruction is the valid control transfer point, not cause the first exception to be raised.
2. The processor of claim 1 , wherein in response to the determination the target instruction is the valid control transfer point, the value of the two bit field is to be replaced with a value of zero.
3. The processor of claim 1 , wherein the determination whether the target instruction is the valid control transfer point is evaluated at decode.
4. The processor of claim 1 , wherein the processor is to enter a first state in response to the first indirect control transfer instruction, and wherein the processor is to exit the first state in response to the determination the target instruction is the valid control transfer point.
5. The processor of claim 1 , further comprising another storage to store a plurality of bits to indicate whether use of the third circuitry to determine whether the target instruction is the valid control transfer point is enabled or disabled.
6. The processor of claim 1 , wherein the first indirect control transfer instruction is a call instruction.
7. The processor of claim 1 , further comprising a retirement unit to cause the first exception to be raised.
8. The processor of claim 1 , wherein the control transfer termination instruction is associated with neither a source operand nor a destination operand.