Methods, systems, and apparatuses for precise last branch record event logging
Systems, methods, and apparatuses relating to circuitry to implement precise last branch record event logging in a processor are described. In one embodiment, a hardware processor core includes an execution circuit to execute instructions, a retirement circuit to retire executed instructions, a status register, and a last branch record circuit to, in response to retirement by the retirement circuit of a first taken branch instruction, start a cycle timer and a performance monitoring event counter, and in response to retirement by the retirement circuit of a second taken branch instruction, that is a next taken branch instruction in program order after the first taken branch instruction, write values from the cycle timer and the performance monitoring event counter into a first entry in the status register and clear the values from the cycle timer and the performance monitoring event counter.
1. An apparatus comprising:
an execution circuit to execute instructions;
a retirement circuit to retire executed instructions;
a status register; and
a last branch record circuit to:
in response to retirement by the retirement circuit of a first taken branch instruction, start a cycle timer and a performance monitoring event counter that is distinct from the cycle timer, and
in response to retirement by the retirement circuit of a second taken branch instruction, that is a next taken branch instruction in program order after the first taken branch instruction, write values from the cycle timer and the performance monitoring event counter into a first entry in the status register and clear the values from the cycle timer and the performance monitoring event counter.
2. The apparatus of claim 1 , wherein the last branch record circuit is to:
in response to retirement by the retirement circuit of the second taken branch instruction, start the cycle timer and the performance monitoring event counter after the clear, and
in response to retirement by the retirement circuit of a third taken branch instruction, that is a next taken branch instruction in program order after the second taken branch instruction, write values from the cycle timer and the performance monitoring event counter into a second entry in the status register and clear the values from the cycle timer and the performance monitoring event counter.
3. The apparatus of claim 1 , further comprising a cache, wherein the last branch record circuit is to update a first counter of the performance monitoring event counter for a hit in the cache for an instruction between the first taken branch instruction and the second taken branch instruction in program order.
4. The apparatus of claim 3 , further comprising a translation lookaside buffer, wherein the last branch record circuit is to update a second counter of the performance monitoring event counter for a miss in the translation lookaside buffer for an instruction between the first taken branch instruction and the second taken branch instruction in program order.
5. The apparatus of claim 1 , wherein the execution circuit is to, in response to execution of a capabilities instruction, load a value into a register of the apparatus that indicates a number of counters of the performance monitoring event counter.
6. The apparatus of claim 1 , wherein the performance monitoring event counter comprises a plurality of counters for different performance monitoring events, and, in response to retirement by the retirement circuit of the second taken branch instruction, the last branch record circuit is further to write an instruction pointer of the first taken branch instruction and an instruction pointer of a target address of the first taken branch instruction into the first entry of the status register with the values of the plurality of counters.
7. The apparatus of claim 1 , wherein, in response to retirement by the retirement circuit of the second taken branch instruction, the last branch record circuit is further to write an instruction pointer of the first taken branch instruction and an instruction pointer of a target address of the first taken branch instruction into the first entry of the status register.
8. The apparatus of claim 1 , further comprising a command register comprising a plurality of bits, wherein the performance monitoring event counter comprises a plurality of counters for different performance monitoring events, and, when a corresponding bit is set in the command register, enables the performance monitoring event counter to count a corresponding performance monitoring event.
9. A method comprising:
executing instructions with an execution circuit of a processor core;
retiring executed instructions with a retirement circuit of the processor core;
in response to retirement by the retirement circuit of a first taken branch instruction, starting a cycle timer and a performance monitoring event counter, that is distinct from the cycle timer, by a last branch record circuit of the processor core; and
in response to retirement by the retirement circuit of a second taken branch instruction, that is a next taken branch instruction in program order after the first taken branch instruction, writing values from the cycle timer and the performance monitoring event counter into a first entry in a status register of the processor core and clearing the values from the cycle timer and the performance monitoring event counter by the last branch record circuit.
10. The method of claim 9 , further comprising:
in response to retirement by the retirement circuit of the second taken branch instruction, starting the cycle timer and the performance monitoring event counter by the last branch record circuit after the clearing; and
in response to retirement by the retirement circuit of a third taken branch instruction, that is a next taken branch instruction in program order after the second taken branch instruction, writing values from the cycle timer and the performance monitoring event counter into a second entry in the status register and clearing the values from the cycle timer and the performance monitoring event counter by the last branch record circuit.
11. The method of claim 9 , further comprising updating a first counter of the performance monitoring event counter for a hit in a cache of the processor core for an instruction between the first taken branch instruction and the second taken branch instruction in program order by the last branch record circuit.
12. The method of claim 11 , further comprising updating a second counter of the performance monitoring event counter for a miss in a translation lookaside buffer of the processor core for an instruction between the first taken branch instruction and the second taken branch instruction in program order by the last branch record circuit.
13. The method of claim 9 , further comprising executing a capabilities instruction with the execution circuit to load a value into a register of the processor core that indicates a number of counters of the performance monitoring event counter.
14. The method of claim 9 , wherein the performance monitoring event counter comprises a plurality of counters for different performance monitoring events, and, in response to retirement by the retirement circuit of the second taken branch instruction, the method further comprising writing an instruction pointer of the first taken branch instruction and an instruction pointer of a target address of the first taken branch instruction into the first entry of the status register with the values of the plurality of counters by the last branch record circuit.
15. The method of claim 9 , wherein, in response to retirement by the retirement circuit of the second taken branch instruction, further comprising writing an instruction pointer of the first taken branch instruction and an instruction pointer of a target address of the first taken branch instruction into the first entry of the status register by the last branch record circuit.
16. The method of claim 9 , wherein the performance monitoring event counter comprises a plurality of counters for different performance monitoring events, and the method further comprises, when a corresponding bit is set in a plurality of bits of a command register of the processor core, enabling the performance monitoring event counter to count a corresponding performance monitoring event.
17. An apparatus comprising:
an execution circuit to execute instructions;
a status register; and
a last branch record circuit to:
in response to a first taken branch instruction, start a cycle timer and a performance monitoring event counter that is distinct from the cycle timer, and
in response to a second taken branch instruction, that is a next taken branch instruction in program order after the first taken branch instruction, write values from the cycle timer and the performance monitoring event counter into a first entry in the status register and clear the values from the cycle timer and the performance monitoring event counter.
18. The apparatus of claim 17 , wherein the last branch record circuit is to:
in response to the second taken branch instruction, start the cycle timer and the performance monitoring event counter after the clear, and
in response to a third taken branch instruction, that is a next taken branch instruction in program order after the second taken branch instruction, write values from the cycle timer and the performance monitoring event counter into a second entry in the status register and clear the values from the cycle timer and the performance monitoring event counter.
19. The apparatus of claim 17 , further comprising a cache, wherein the last branch record circuit is to update a first counter of the performance monitoring event counter for a hit in the cache for an instruction between the first taken branch instruction and the second taken branch instruction in program order.
20. The apparatus of claim 19 , further comprising a translation lookaside buffer, wherein the last branch record circuit is to update a second counter of the performance monitoring event counter for a miss in the translation lookaside buffer for an instruction between the first taken branch instruction and the second taken branch instruction in program order.
21. The apparatus of claim 17 , wherein the execution circuit is to, in response to execution of a capabilities instruction, load a value into a register of the apparatus that indicates a number of counters of the performance monitoring event counter.
22. The apparatus of claim 17 , wherein the performance monitoring event counter comprises a plurality of counters for different performance monitoring events, and, in response to the second taken branch instruction, the last branch record circuit is further to write an instruction pointer of the first taken branch instruction and an instruction pointer of a target address of the first taken branch instruction into the first entry of the status register with the values of the plurality of counters.
23. The apparatus of claim 17 , wherein, in response to the second taken branch instruction, the last branch record circuit is further to write an instruction pointer of the first taken branch instruction and an instruction pointer of a target address of the first taken branch instruction into the first entry of the status register.
24. The apparatus of claim 17 , further comprising a command register comprising a plurality of bits, wherein the performance monitoring event counter comprises a plurality of counters for different performance monitoring events, and, when a corresponding bit is set in the command register, enables the performance monitoring event counter to count a corresponding performance monitoring event.