Spin-orbit-torque magnetoresistive random-access memory
A spin-orbit torque magnetoresistive random-access memory device formed by fabricating a spin-Hall-effect (SHE) layer above and in electrical contact with a transistor, forming a spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) cell stack disposed above and in electrical contact with the SHE rail, wherein the SOT-MRAM cell stack comprises a free layer, a tunnel junction layer, a reference layer, and a diode structure, forming a write line disposed in electrical contact with the SHE rail, forming a protective dielectric layer covering a portion of the SOT-MRAM cell stack, and forming a read line disposed above and adjacent to the diode structure.
1. An MRAM (magnetoresistive random-access memory) structure comprising:
a spin-Hall-effect (SHE) rail;
an spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) cell stack disposed above and in electrical contact with the SHE rail, wherein the SOT-MRAM cell stack comprises a free layer, a tunnel junction layer, a reference layer, and a diode structure;
a write line disposed in electrical contact with the SHE rail; and
a read line disposed above and adjacent to the diode structure.
2. The MRAM structure according to claim 1 , wherein the SHE rail is disposed in electrical contact with a transistor.
3. The MRAM structure according to claim 1 , wherein diode structure comprises a metal-oxide-metal layered structure.
4. The MRAM structure according to claim 1 , wherein the free layer is disposed adjacent to the SHE rail.
5. The MRAM structure according to claim 1 , wherein the write line is disposed above the SHE rail.
6. The MRAM structure according to claim 1 , wherein the write line is disposed below the SHE rail.
7. The MRAM structure according to claim 1 , wherein the SHE rail comprises a material selected from the group consisting of Ta, Pt, W, Jr, and combinations thereof.
8. The MRAM structure according to claim 1 , wherein the diode structure comprises a TiO 2 /Ti layer stack.
9. An MRAM (magnetoresistive random-access memory) structure comprising:
a spin-Hall-effect (SHE) rail disposed in electrical contact with a transistor;
an spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) cell stack disposed above and in electrical contact with the SHE rail, wherein the SOT-MRAM cell stack comprises a free layer, a tunnel junction layer, a reference layer, and a diode structure;
a write line disposed in electrical contact with the SHE rail; and
a read line disposed above and adjacent to the diode structure.
10. The MRAM structure according to claim 9 , wherein diode structure comprises a metal-oxide-metal layered structure.
11. The MRAM structure according to claim 9 , wherein the free layer is disposed adjacent to the SHE rail.
12. The MRAM structure according to claim 9 , wherein the write line is disposed above the SHE rail.
13. The MRAM structure according to claim 9 , wherein the write line is disposed below the SHE rail.
14. The MRAM structure according to claim 9 , wherein the SHE rail comprises a material selected from the group consisting of Ta, Pt, W, Ir, and combinations thereof.
15. The MRAM structure according to claim 9 , wherein the diode structure comprises a TiO 2 /Ti layer stack.
16. A method of fabricating a semiconductor device, the method comprising:
forming a spin-Hall-effect (SHE) layer above and in electrical contact with a transistor;
forming a spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) cell stack disposed above and in electrical contact with the SHE rail, wherein the SOT-MRAM cell stack comprises a free layer, a tunnel junction layer, a reference layer, and a diode structure;
forming a write line disposed in electrical contact with the SHE rail;
forming a protective dielectric layer covering a portion of the SOT-MRAM cell stack; and
forming a read line disposed above and adjacent to the diode structure.
17. The method of fabricating a semiconductor structure according to claim 16 , wherein diode structure comprises a metal-oxide-metal layered structure.
18. The method of fabricating a semiconductor structure according to claim 16 , wherein the free layer is disposed adjacent to the SHE rail.
19. The method of fabricating a semiconductor structure according to claim 16 , wherein the write line is disposed above the SHE rail.
20. The method of fabricating a semiconductor structure according to claim 16 , wherein the write line is disposed below the SHE rail.