Dynamic memory with long retention time
The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a DRAM cell with an access transistor and a storage capacitor, and a word-line coupled to a gate terminal of the access transistor. During the period between the word-line being selected to turn on the access transistor and the word line being unselected to turn off the access transistor, either a first voltage level or a second voltage level is stored in the DRAM cell, wherein the first voltage level is higher than a voltage level of a signal ONE utilized in the DRAM, and the second voltage level is lower than a voltage level of a signal ZERO utilized in the DRAM.
1. A DRAM chip, comprising:
a first group of DRAM cells, each DRAM cell comprising an access transistor and a storage capacitor; and
a first group of sense amplifiers electrically coupled to the first group of DRAM cells;
wherein a retention time of the DRAM chip at a first reference temperature is the same or substantially the same as that at a second reference temperature, and is the same or substantially the same as that at a third reference temperature, wherein the first reference temperature is less than the second reference temperature, and the second reference temperature is less than the third reference temperature, the first reference temperature is not less than 75° C.,
wherein the difference between the first reference temperature and the second reference is not less than 10° C.
2. The DRAM chip in claim 1 , the first reference temperature is 85° C., the second reference temperature is 95° C., and the third reference temperature is 105° C.
3. A DRAM chip, comprising:
a first group of DRAM cells, each DRAM cell comprising an access transistor and a storage capacitor; and
a first group of sense amplifiers electrically coupled to the first group of DRAM cells;
wherein a retention time of the DRAM chip at a first reference temperature is the same or substantially the same as that at a second reference temperature, and is the same or substantially the same as that at a third reference temperature, wherein the first reference temperature is less than the second reference temperature, and the second reference temperature is less than the third reference temperature,
wherein the retention time of the DRAM chip is calculated according to an average retention time of the first group of DRAM cells based on 3-Sigma.
4. The DRAM chip in claim 3 , wherein the retention time of the DRAM chip is approximate to 130 ms.