Semiconductor device structure with uniform threshold voltage distribution and method of forming the same

1. A method, comprising:

forming a fin structure extending above a dielectric isolation structure disposed over a substrate, the dielectric isolation structure laterally surrounding a bottom portion of the fin structure;

forming a semiconductor liner layer including a dopant over the fin structure;

forming a first capping layer to physically contact a bottom portion of the semiconductor liner layer and the dielectric isolation structure, the bottom portion of the semiconductor liner layer laterally surrounding a lower portion of the fin structure;

forming a second capping layer to physically contact an upper portion of the semiconductor liner layer, the upper portion of the semiconductor liner layer laterally surrounding an upper portion of the fin structure; and

annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing causing the dopant of the semiconductor liner layer to diffuse into the fin structure, wherein an average dopant concentration in a lower portion of the fin structure is different from an average dopant concentration in an upper portion of the channel region.

2. The method of claim 1 , after the annealing the fin structure, further comprising

forming a gate structure over a channel region of the fin structure; and

forming a source feature and a drain feature over the fin structure.

3. The method of claim 2 , further comprising etching to remove the first capping layer, the second capping layer, and the semiconductor liner layer, the etching forming a trimmed fin structure, wherein the forming a gate structure includes forming the gate structure over the trimmed fin structure.

4. The method of claim 1 , wherein the dopant includes germanium, and wherein the fin structure includes silicon.

5. The method of claim 1 , wherein a difference between the average dopant concentration in the lower portion of the fin structure and the average dopant concentration in the upper portion of the fin structure is in a range from about 3% to about 10%.

6. The method of claim 1 , wherein

the first capping layer is a nitride-containing layer, and wherein the second capping layer is an oxide-containing layer; and

after the annealing, a core region of the upper portion of the fin structure is free from the dopant, and wherein the average dopant concentration in the lower portion of the fin structure is substantially uniform.

7. The method of claim 1 , wherein

the first capping layer is an oxide-containing layer, and wherein the second capping layer is a nitride-containing layer; and

after the annealing, the average dopant concentration in the upper portion of the fin structure is substantially uniform, and wherein a core region of the lower portion of the fin structure is free from the dopant.

8. The method of claim 1 , wherein the bottom portion of the fin structure is free from the dopant.

9. A method, comprising:

forming a fin structure extending above a dielectric isolation structure disposed over a substrate;

forming a semiconductor liner layer over the fin structure;

performing an annealing process to drive a dopant contained in the semiconductor liner layer into the fin structure;

etching to remove the semiconductor liner layer, the etching forming a trimmed fin structure;

forming a first gate structure over a channel region of the trimmed fin structure; and

forming a source feature and a drain feature on the trimmed fin structure.

10. The method of claim 9 , further comprising replacing the first gate structure with a second gate structure that include metal.

11. The method of claim 9 , performing an annealing process, further comprising

forming a first capping layer to physically contact a bottom portion of the semiconductor liner layer; and

forming a second capping layer to physically contact an upper portion of the semiconductor liner layer, wherein

wherein an average dopant concentration in a bottom portion of the fin structure is different from an average dopant concentration in an upper portion of the fin structure.

12. The method of claim 11 , further comprising etching to remove the first capping layer, the second capping layer before the forming a first gate structure.

13. The method of claim 11 , wherein a difference between the average dopant concentration in the bottom portion of the fin structure and the average dopant concentration in the upper portion of the fin structure is in a range from about 3% to about 10%.

14. The method of claim 11 , wherein

the first capping layer is a nitride-containing layer, and wherein the second capping layer is an oxide-containing layer; and

after the annealing, a core region of the upper portion of the channel region is free from the dopant, and wherein the average dopant concentration in the bottom portion of the channel region is substantially uniform.

15. The method of claim 11 , wherein

the first capping layer is an oxide-containing layer, and wherein the second capping layer is a nitride-containing layer; and

after the annealing, the average dopant concentration in the upper portion of the channel region is substantially uniform, and wherein a core region of the lower portion of the channel region is free from the dopant.

16. The method of claim 9 , wherein the dopant includes germanium, and wherein the fin structure includes silicon.

17. A method, comprising:

forming a fin structure extending above a dielectric isolation structure disposed over a substrate, the fin structure including a first fin and a second fin;

forming a patterned dielectric layer covering the second fin, the patterned dielectric layer includes an opening to expose the first fin;

selectively growing a semiconductor liner layer on the first fin through the opening of the patterned dielectric layer;

forming a first capping layer over the dielectric isolation structure, the first capping layer laterally surrounding a lower portion of the semiconductor liner layer, the lower portion of the semiconductor liner layer laterally surrounding a lower portion of the first fin;

forming a second capping layer over an upper portion of the semiconductor liner layer, the upper portion of the semiconductor liner layer laterally surrounding an upper portion of the first fin, the second capping layer being a material different from the first capping layer; and

annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon to drive a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in the lower portion of the fin structure is different from a dopant concentration profile in the upper portion of the fin structure.

18. The method of claim 17 , further comprising:

after the annealing, removing the first capping layer and the second capping layer to expose the semiconductor liner layer and a top surface of the dielectric isolation structure;

trimming the fin structure to remove the semiconductor liner layer, the trimming resulting in a trimmed fin structure with substantially vertical sidewalls;

forming a gate stack over the trimmed fin structure; and

forming a source feature and a drain feature on the trimmed fin structure.

19. The method of claim 17 , wherein

the first capping layer is a nitride-containing layer, and wherein the second capping layer is an oxide-containing layer; and

after the annealing, a center region of the upper portion of the fin structure is free from the dopant from the semiconductor liner layer, and wherein the dopant concentration profile in the lower portion of the fin structure is substantially uniform.

20. The method of claim 17 , wherein

the first capping layer is an oxide-containing layer, and wherein the second capping layer is a nitride-containing layer; and

after the annealing, the dopant concentration profile in the upper portion of the fin structure is substantially uniform, and wherein a center region of the lower portion of the fin structure is free from the dopant from the semiconductor liner layer.