Memory controller and operating method thereof
A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating device information on the identified memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.
1. A memory controller for controlling a plurality of memory devices coupled through a plurality of channels, the memory controller comprising:
a dummy manager configured to output a request for controlling a dummy pulse to be applied to channels of memory devices in response to device information among the plurality of channels, the device information identifying the memory devices to perform operations corresponding to requests from a host; and
a dummy pulse generator configured to sequentially apply the dummy pulse to the channels of the memory devices identified by the device information, in response to the request for controlling the dummy pulse.
2. The memory controller of claim 1 , wherein the dummy manager outputs a dummy pulse generation request for requesting the dummy pulse to be applied to the channels of the memory devices before the memory devices start operations.
3. The memory controller of claim 1 , wherein the dummy pulse generator applies the dummy pulse to any one channel among the channels of any one of the memory devices according to the device information.
4. The memory controller of claim 1 , further comprising:
a request checker configured to generate the device information;
an enable signal generator configured to generate chip enable signals for selecting the plurality of memory devices; and
a command queue group including command queues respectively corresponding to the plurality of memory devices.
5. The memory controller of claim 1 , wherein the dummy manager receives chip enable signals respectively corresponding to the memory devices according to the device information, and determines memory devices to end operations, based on chip enable signals in a high state among the received chip enable signals.
6. The memory controller of claim 5 , wherein the dummy manager outputs a command queue level request for determining command queue levels of memory devices corresponding to chip enable signals in the high state, and
wherein the command queue group outputs the command queue levels corresponding to the command queue level request.
7. The memory controller of claim 5 , wherein the dummy manager determines to apply the dummy pulse to channels coupled to the memory devices corresponding to the chip enable signals in the high state.
8. The memory controller of claim 1 , wherein the dummy manager determines to interrupt the dummy pulse applied to any one of the channels.
9. The memory controller of claim 1 , wherein the dummy manager determines whether a number of memory devices of which command queue levels has have a value is two or more.
10. The memory controller of claim 1 , wherein the dummy manager determines to apply the dummy pulse to the channels coupled to the memory devices corresponding to chip enable signals in a high state and interrupts the dummy pulse applied to channels coupled to the memory devices of which command queue levels have a value.
11. A storage system comprising:
a plurality of memory devices including a non-volatile memory; and
a controller configured to control the plurality of memory devices, the controller comprising:
a dummy manager configured to output a request for controlling a dummy pulse to be applied to channels of memory devices in response to device information among the plurality of channels, the device information identifying the memory devices to perform operations corresponding to requests from a host; and
a dummy pulse generator configured to sequentially apply the dummy pulse to the channels of the memory devices identified by the device information, in response to the request for controlling the dummy pulse.
12. The storage system of claim 11 , wherein the dummy manager outputs a dummy pulse generation request for requesting the dummy pulse to be applied to the channels of the memory devices before the memory devices start operations.
13. The storage system of claim 11 , wherein the dummy pulse generator applies the dummy pulse to any one channel among the channels of any one of the memory devices according to the device information.
14. The storage system of claim 11 , further comprising:
a request checker configured to generate the device information;
an enable signal generator configured to generate chip enable signals for selecting the plurality of memory devices; and
a command queue group including command queues respectively corresponding to the plurality of memory devices.
15. The storage system of claim 11 , wherein the dummy manager receives chip enable signals respectively corresponding to the memory devices according to the device information, and determines memory devices to end operations, based on chip enable signals in a high state among the received chip enable signals.
16. The storage system of claim 14 , wherein the dummy manager outputs a command queue level request for determining command queue levels of memory devices corresponding to chip enable signals in a high state, and
wherein the command queue group outputs the command queue levels corresponding to the command queue level request.
17. The storage system of claim 15 , wherein the dummy manager determines to apply the dummy pulse to channels coupled to the memory devices corresponding to the chip enable signals in the high state.
18. The storage system of claim 11 , wherein the dummy manager determines to interrupt the dummy pulse applied to any one of the channels.
19. The storage system of claim 11 , wherein the dummy manager determines whether a number of memory devices of which command queue levels have a value is two or more.
20. The storage system of claim 11 , wherein the dummy manager determines to apply the dummy pulse to the channels coupled to the memory devices corresponding to chip enable signals in a high state and interrupts the dummy pulse applied to channels coupled to the memory devices of which command queue levels have a value.