Memory controller and operating method thereof
A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating device information on the identified memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.
1. A controller for controlling a plurality of memory devices, the controller comprising:
a request checker configured to select, based on a request to perform an operation, one of the memory devices; and
a dummy pulse generator configured to adjust, by applying a dummy pulse, current supplied to the selected memory device to control current consumption of the plurality of memory devices.
2. The controller of claim 1 , wherein the selected memory device is a first memory device, and
wherein the dummy pulse generator increases current supplied to the first memory device and a second memory device to reach a peak when the first memory device and the second memory device respectively start performing operations at the same time.
3. The controller of claim 1 , wherein the selected memory device is a first memory device and the request is a first request,
wherein the request checker selects, based on a second request to perform the operation, a second memory device from the memory devices,
wherein the dummy pulse generator sequentially adjusts, by sequentially applying the dummy pulse to the first and second memory devices, current supplied to the first and second memory devices, and
wherein the first request and the second request are received from a host.
4. The controller of claim 1 , wherein the request checker identifies a memory device corresponding to the request.
5. The controller of claim 4 , further comprising:
a dummy manager configured to generate device information on the identified memory device to perform an operation corresponding to the request.
6. The controller of claim 1 , further comprising:
a dummy manager configured to output a request for generating a dummy pulse to be applied to a channel of the selected memory device.
7. The controller of claim 1 , wherein the dummy pulse generator applies a dummy pulse to a channel coupled to the selected memory device for a set duration.
8. The controller of claim 1 , further comprising:
a clock signal generator configured to determine whether to apply an initial frequency scaling of a clock signal based on a duration of an idle time interval of a memory device.
9. The controller of claim 1 , further comprising:
an idle time monitor configured to monitor an idle time interval of a memory device, the idle time interval being an interval between an end time of a previous operation of the memory device and a start time of a current operation of the memory device.
10. The controller of claim 1 , further comprising:
a clock signal generator configured to generate a clock signal based on an idle time interval of the selected memory device and output the clock signal to the selected memory device through a channel of the selected memory device to perform a current operation.
11. The controller of claim 1 , further comprising:
a clock signal generator configured to generate a clock signal during an initial frequency scaling period of a current operation, based on a comparison result of an idle time interval of the selected memory device with a threshold time interval.
12. The controller of claim 1 , further comprising:
a clock signal generator configured to generate a first clock having a plurality of modulation sections by performing a modulation operation on a source clock and output the first clock to the selected memory device.
13. The controller of claim 12 , further comprising:
a modulation circuit configured to perform the modulation operation using a plurality of frequencies.
14. The controller of claim 13 , further comprising:
a modulation circuit configured to perform the modulation operation and receive read data in response to a second clock.
15. A controller for controlling a plurality of memory devices, the controller comprising:
a request checker configured to identify, based on a request to perform an operation, one of the plurality of memory devices; and
a dummy pulse generator configured to adjust, by applying a dummy pulse of a set to an unidentified memory device, current supplied to the unidentified memory device to control current consumption of the plurality of memory devices.
16. The controller of claim 15 , wherein the dummy pulse generator increases current supplied to the unidentified memory device and another unidentified memory device to reach a peak when the identified memory device starts performing the operation corresponding to the request at a time.
17. The controller of claim 15 , further comprising:
a dummy manager configured to output a request for generating a dummy pulse to a channel and applying the dummy pulse to a channel coupled to the unidentified memory device.
18. The controller of claim 15 , further comprising:
a clock signal generator configured to:
determine whether to apply an initial frequency scaling of a clock signal based on a duration of an idle time interval of a memory device, or
generate the clock signal during an initial frequency scaling period of a current operation, based on the duration of the idle time interval of the identified one of the memory devices, or
generate the clock signal based on the idle time interval of the identified memory device and output the clock signal to the unidentified memory device through a channel coupled to the identified memory device performing the current operation.
19. The controller of claim 15 , further comprising:
a clock signal generator configured to generate a first clock having a plurality of modulation sections by performing a modulation operation on a source clock and output the first clock to the identified one of the plurality of memory devices, or
a modulation circuit configured to:
perform the modulation operation using a plurality of frequencies, or
perform the modulation operation and receive read data in response to a second clock.
20. The controller of claim 15 , wherein the unidentified memory device is a first unidentified memory device,
wherein the dummy pulse generator sequentially adjusts, by sequentially applying the dummy pulse of a set duration to the first unidentified memory device and a second unidentified memory device, current supplied to the first unidentified memory device and the second unidentified memory device, and increases current supplied to the identified memory device, the first unidentified memory device, and the second unidentified memory device to reach a peak when the identified memory device starts performing the operation corresponding to the request at a time.