Vector floating-point classification
A method to classify source data in a processor in response to a vector floating-point classification instruction includes specifying, in respective fields of the vector floating-point classification instruction, a source register containing the source data and a destination register to store classification indications for the source data. The source register includes a plurality of lanes that each contains a floating-point value and the destination register includes a plurality of lanes corresponding to the lanes of the source register. The method further includes executing the vector floating-point classification instruction by, for each lane in the source register, classifying the floating-point value in the lane to identify a type of the floating-point value, and storing a value indicative of the identified type in the corresponding lane of the destination register.
1. A processor comprising:
a functional unit; and
a set of vector registers coupled to the functional units, wherein the processor is configured to:
store a first vector that includes a set of floating-point values in a first vector register of the set of vector registers;
receive an instruction that specifies the first vector register and a second vector register of the set of vector registers; and
based on the instruction, cause the functional unit to:
classify each value of the set of floating-point values of the first vector; and
store a second vector in the second vector register, wherein the second vector includes a set of elements that each indicate a respective classification of a respective value of the set of floating-point values of the first vector.
2. The processor of claim 1 , wherein the functional unit is configured to classify each value of the set of floating-point values of the first vector by determining whether the respective value represents a zero value, a subnormal value, a normal value, an infinite value, a not a number (NaN) value, a quiet NaN (QNaN) value, or a signaling NaN (SNaN) value.
3. The processor of claim 2 , wherein the functional unit is configured to indicate:
a zero value in the first vector using a value of 0 in the second vector;
a subnormal value in the first vector using a value of 1 in the second vector;
a normal value in the first vector using a value of 2 in the second vector;
an infinite value in the first vector using a value of 3 in the second vector;
a NaN value in the first vector using a value of 4 in the second vector; and
a SNaN value in the first vector using a value of 8 in the second vector.
4. The processor of claim 1 further comprising a set of functional units each configured to classify the set of floating-point values of the first vector, wherein the instruction specifies the functional unit from among the set of functional units.
5. The processor of claim 1 further comprising:
a scalar datapath; and
a vector datapath that includes the functional unit, wherein the instruction specifies the vector datapath.
6. The processor of claim 1 , wherein the instruction specifies whether the set of floating-point values are single precision or double precision.
7. The processor of claim 1 , wherein:
each value of the set of floating-point values includes a respective exponent; and
the functional unit is configured to determine whether a respective value of the set of floating-point values represents either an infinite value or a not-a-number value based on the respective exponent.
8. The processor of claim 7 , wherein:
each value of the set of floating-point values includes a respective fraction; and
the functional unit is configured to distinguish whether a respective value of the set of floating-point values represents the infinite value or the not-a-number value based on the respective fraction.
9. The processor of claim 1 , wherein:
a size of the first vector register is different from a size of the second vector register.
10. The processor of claim 1 , wherein:
the first vector register has a size of 512 bits.
11. The processor of claim 10 , wherein:
the second vector register has a size of 64 bits.
12. A method comprising:
storing a first vector in a first vector register, wherein the first vector includes a set of floating-point values;
receiving an instruction that specifies a classification operation and the first vector register; and
based on the instruction, classifying each value of the set of floating-point values of the first vector to produce a second vector that includes a set of elements that each indicate a respective classification of a respective value of the set of floating-point values of the first vector.
13. The method of claim 12 , wherein:
the instruction further specifies a second vector register; and
the method further comprises storing the second vector in the second vector register.
14. The method of claim 12 , wherein the classifying includes determining whether each value of the set of floating-point values determines whether the respective value represents a zero value, a subnormal value, a normal value, an infinite value, a not a number (NaN) value, a quiet NaN (QNaN) value, or a signaling NaN (SNaN) value.
15. The method of claim 12 , wherein:
the instruction specifies a functional unit from among a set of functional units; and
the classifying is performed by the functional unit.
16. The method of claim 12 , wherein the instruction specifies whether the set of floating-point values are single precision or double precision.
17. The method of claim 12 , wherein:
each value of the set of floating-point values includes a respective exponent; and
the classifying includes determining whether a respective value of the set of floating-point values represents either an infinite value or a not-a-number value based on the respective exponent.
18. The method of claim 17 , wherein:
each value of the set of floating-point values includes a respective fraction; and
the classifying includes distinguishing whether a respective value of the set of floating-point values represents the infinite value or the not-a-number value based on the respective fraction.
19. The method of claim 17 , wherein a size of the first vector is different from a size of the second vector.
20. The method of claim 17 , wherein the first vector has a size of 512 bits and the second vector has a size of 64 bits.