IP Library Granted Patent US 11,804,403
Granted Patent B2
US 11,804,403 · App. 17/382,379 · Granted Oct 31, 2023

Semiconductor structure and method for forming the same

Inventors: Ji He Huang (Suzhou, CN); Wen Yi Tan (Fujian, CN)
Assignee: United Semiconductor (Xiamen) Co., Ltd.
H01L21/7682H01L21/76819H01L21/76835H01L23/5283H01L23/53295
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Quick Facts
Patent No.
US 11,804,403
App. No.
17/382,379
Granted
Oct 31, 2023
Kind
B2
Abstract

A semiconductor structure and a method for forming the same are disclosed. The method includes the steps of forming a first dielectric layer on a substrate, forming a plurality of first interconnecting structures in the first dielectric layer, forming at least a trench in the first dielectric layer and between the first interconnecting structures, performing a sputtering deposition process to form a second dielectric layer on the first dielectric layer, wherein the second dielectric layer at least partially seals an air gap in the trench, and forming a third dielectric layer on the second dielectric layer.

Claims (43)

1. A method for forming a semiconductor structure, comprising:

forming a first dielectric layer on a substrate;

forming a plurality of first interconnecting structures in the first dielectric layer;

forming at least a trench in the first dielectric layer between the plurality of first interconnecting structures, wherein none of the plurality of first interconnecting structures is exposed from the trench;

performing a sputtering deposition process to form a second dielectric layer on the first dielectric layer and at least partially sealing an air gap in the trench; and

forming a third dielectric layer on the second dielectric layer.

2. The method for forming a semiconductor structure according to claim 1 , wherein the second dielectric layer comprises silicon oxide.

3. The method for forming a semiconductor structure according to claim 1 , wherein the third dielectric layer comprises a low-k dielectric material.

4. The method for forming a semiconductor structure according to claim 1 , wherein the first dielectric layer comprises a low-k dielectric material.

5. The method for forming a semiconductor structure according to claim 1 , wherein the air gap is completely sealed by the second dielectric layer.

6. The method for forming a semiconductor structure according to claim 1 , wherein the air gap is partially sealed by the second dielectric layer and completely sealed by the third dielectric layer.

7. The method for forming a semiconductor structure according to claim 1 , further comprising:

performing a planarization process to the third dielectric layer; and

forming a plurality of second interconnecting structures through the third dielectric layer and the second dielectric layer to electrically connect to the first interconnecting structures.

8. The method for forming a semiconductor structure according to claim 1 , wherein the step of forming the trench comprises:

forming a hard mask layer on the first dielectric layer;

forming a photoresist layer on the hard mask layer and a first opening in the photoresist layer to expose a portion of the hard mask layer;

through the first opening, etching the hard mask layer to form a second opening in the hard mask layer;

through the first opening and the second opening, etching the first dielectric layer to form the trench; and

removing the photoresist layer and the hard mask layer completely.

9. The method for forming a semiconductor structure according to claim 8 , wherein the hard mask layer comprises titanium nitride (TiN).

10. A method for forming a semiconductor structure, comprising:

forming a first dielectric layer on a substrate;

forming a plurality of first interconnecting structures in the first dielectric layer;

forming at least a trench in the first dielectric layer between the plurality of first interconnecting structures, wherein none of the plurality of first interconnecting structures is exposed from the trench;

performing a sputtering deposition process to form a second dielectric layer on the first dielectric layer and sealing an air gap in the trench; and

performing a planarization process to the second dielectric layer.

11. The method for forming a semiconductor structure according to claim 10 , wherein the second dielectric layer comprises silicon oxide.

12. The method for forming a semiconductor structure according to claim 10 , further comprising forming a plurality of second interconnecting structures through the second dielectric layer to electrically connect to the first interconnecting structures.

13. The method for forming a semiconductor structure according to claim 10 , wherein the step of forming the trench comprises:

forming a hard mask layer on the first dielectric layer;

forming a photoresist layer on the hard mask layer and a first opening in the photoresist layer to expose a portion of the hard mask layer;

through the first opening, etching the hard mask layer to form a second opening in the hard mask layer;

through the first opening and the second opening, etching the first dielectric layer to form the trench; and

removing the photoresist layer and the hard mask layer completely.

14. The method for forming a semiconductor structure according to claim 13 , wherein the hard mask layer comprises titanium nitride (TiN).

15. A semiconductor structure, comprising:

a first dielectric layer disposed on a substrate;

a plurality of first interconnecting structures disposed in the first dielectric layer;

a silicon oxide layer disposed on the first dielectric layer and sealing an air gap between the plurality of first interconnecting structures, wherein the silicon oxide layer is completely separated from the plurality of first interconnecting structures by the first dielectric layer; and

a low-k dielectric layer disposed on the silicon oxide layer.

16. The semiconductor structure according to claim 15 , wherein the air gap is completely sealed by the silicon oxide layer.

17. The semiconductor structure according to claim 15 , wherein the air gap is completely sealed by the silicon oxide layer and the low-k dielectric layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2021
From: HUANG, JI HE; TAN, WEN YI
To: UNITED SEMICONDUCTOR (XIAMEN) CO., LTD.
Reel/Frame 056940/0302 →
Priority Claims (1)
CN 202110652469.3 · Jun 11, 2021 · national
Continuity (1)
Related Publication 20220399226A1 · Dec 15, 2022
Cited By (1)
US 12,334,431