Semiconductor interconnection structures and methods of forming the same
View Patent ↗A first dielectric layer is formed on a semiconductor structure. The first dielectric layer has a hardness higher than 10 GPa and a dielectric constant in a range between 1.0 and 4.0. A trench is formed in the first dielectric layer. A conductive feature is formed in the trench in contact with the semiconductor structure. A second dielectric layer is formed over the first dielectric layer and the conductive feature. A via structure is formed in the second dielectric layer in contact with the conductive feature.
1. A method for forming an interconnection structure, comprising:
forming a conductive layer on a semiconductor structure;
patterning the conductive layer to form a plurality of conductive features on the semiconductor structure;
forming a first dielectric layer between two adjacent conductive features of the plurality of conductive features, wherein the first dielectric layer comprises a silicon oxide carbide (SiOC) based material with ordered structure formed from tetraethyl orthosilicate (TEOS) in an acidic ethanol with a surfactant, and the first dielectric layer has a hardness higher than 10 GPa and a dielectric constant in a range between 1.0 and 4.0;
forming a cap layer on the plurality of conductive features;
forming a second dielectric layer over the cap layer, the first dielectric layer and the plurality of conductive features, wherein the first dielectric layer and the second dielectric layer comprise different materials; and
forming a via structure in the second dielectric layer in contact with the conductive feature.
2. The method of claim 1 , wherein forming the first dielectric layer between two adjacent conductive features of the plurality of conductive features, further comprises:
forming the first dielectric layer having an air gap between two adjacent conductive features of the plurality of conductive features.
3. The method of claim 2 , wherein forming the first dielectric layer having the air gap between two adjacent conductive features of the plurality of conductive features, further comprises:
filling a flowable dielectric material between two adjacent conductive features to generate the air gap within the flowable dielectric material.
4. The method of claim 2 , wherein forming the cap layer on the plurality of conductive features, further comprises:
selectively depositing the cap layer on the plurality of conductive features without covering the first dielectric layer.
5. The method of claim 1 , wherein the first dielectric layer comprises a silicon carbo-nitride (SiCN) based material formed from Si(CH 3 ) 4 with NH 3 at a deposition temperature between 150 degrees Celsius and 425 degrees Celsius, or from SiH 4 with NH 3 and C 2 H 4 at a deposition temperature between 150 degrees Celsius and 425 degrees Celsius.
6. The method of claim 1 , wherein the first dielectric layer comprises a boron carbo-nitride (BCN) based material formed from triethyl borate (TEB) with NH 3 at a deposition temperature between 150 degrees Celsius and 425 degrees Celsius.
7. A method for forming an interconnection structure, comprising:
forming a device layer over a substrate;
forming a conductive layer on the device layer;
forming openings in the conductive layer, each opening exposing a portion of the device layer;
forming a first dielectric layer in the openings, wherein the first dielectric layer has a hardness higher than 10 GPa;
selectively forming a cap layer on the conductive layer, wherein the cap layer is a two-dimensional (2D) material;
forming a second dielectric layer on the cap layer and the first dielectric layer;
forming a trench opening in the second dielectric layer; and
forming a via opening through the second dielectric layer and the cap layer to expose a portion of the conductive layer, wherein the via opening in the cap layer has an extended portion protruding along a horizontal direction perpendicular to a longitudinal direction of the via opening.
8. The method of claim 7 , wherein the first dielectric layer has a dielectric constant in a range between 1.0 and 4.0.
9. The method of claim 7 , wherein the first dielectric layer and the second dielectric layer comprise a material chemically different from each other.
10. The method of claim 7 , wherein the first dielectric layer is formed with an air gap therein.
11. The method of claim 10 , further comprising:
after forming openings in the conductive layer, forming a barrier layer between the conductive layer and the first dielectric layer.
12. The method of claim 11 , wherein the cap layer is in contact with the barrier layer.
13. The method of claim 7 , wherein the first dielectric layer is a silicon carbo-nitride (SiCN) based material or a boron carbo-nitride (BCN) based material.
14. The method of claim 7 , wherein the first dielectric layer is a silicon oxide carbide (SiOC) based material with ordered structure.
15. The method of claim 7 , wherein the 2D material is graphene.
16. The method of claim 7 , further comprising:
subjecting a top surface of the conductive layer to a plasma formed from a hydrogen-based gas, an ammonia-based gas or an argon-based gas.
17. A method for forming an interconnection structure, comprising:
forming a conductive layer over a semiconductor structure;
patterning the conductive layer to form a plurality of conductive features;
forming a first dielectric layer between two adjacent conductive features, wherein the first dielectric layer comprises a silicon oxide carbide (SiOC) based material with ordered structure formed from tetraethyl orthosilicate (TEOS) in an acidic ethanol, and the first dielectric layer has a hardness higher than 10 GPa and a dielectric constant in a range between 1.0 and 4.0;
forming a cap layer over the first dielectric layer and the plurality of conductive features;
forming a second dielectric layer on the cap layer; and
forming a via opening and a trench opening in the second dielectric layer.
18. The method of claim 17 , wherein the via opening is extended through the second dielectric layer and the cap layer, and a portion of the via opening in the second dielectric layer has a first width and a portion of the via opening in the cap layer has a second width different than the first width.
19. The method of claim 17 , wherein the first dielectric layer is formed with an air gap therein.