Semiconductor device
A semiconductor device is provided, including: a semiconductor substrate; a first-conductivity-type drift region provided in the semiconductor substrate; a trench portion provided from an upper surface of the semiconductor substrate to an inside of the semiconductor substrate, and extending in a predetermined extending direction in a plane of the upper surface of the semiconductor substrate; a mesa portion provided in contact with the trench portion in an array direction orthogonal to the extending direction; a second-conductivity-type base region provided in the mesa portion above the drift region and in contact with the trench portion; and a second-conductivity-type floating region provided in the mesa portion below the base region, in contact with the trench portion, and provided in at least a part of the mesa portion in the array direction.
1. A semiconductor device comprising:
a semiconductor substrate;
a first-conductivity-type drift region provided in the semiconductor substrate;
a trench portion provided from an upper surface of the semiconductor substrate to an inside of the semiconductor substrate, and extending in a predetermined extending direction in a plane of the upper surface of the semiconductor substrate;
a mesa portion provided in contact with the trench portion in an array direction orthogonal to the extending direction;
a second-conductivity-type base region provided in the mesa portion above the drift region and in contact with the trench portion; and
a second-conductivity-type floating region provided in the mesa portion below the base region, in contact with the trench portion, and provided in at least a part of the mesa portion in the array direction, wherein
a distance between the base region and the floating region in a depth direction of the semiconductor substrate is twice or more than a width of the base region in the depth direction of the semiconductor substrate.
2. The semiconductor device according to claim 1 , wherein at least a part of the floating region in the depth direction of the semiconductor substrate is provided in contact with a bottom portion of the trench portion.
3. The semiconductor device according to claim 2 , wherein
a remaining portion of the floating region other than at least the part of the floating region in the depth direction of the semiconductor substrate is arranged above the bottom portion of the trench portion.
4. The semiconductor device according to claim 1 , wherein
a ratio of a width from the upper surface of the semiconductor substrate to an upper end of the floating region to a width from the upper surface of the semiconductor substrate to an end of a bottom portion of the trench portion is 70% or more and less than 100%.
5. The semiconductor device according to claim 4 , wherein
the ratio is 80% or more.
6. The semiconductor device according to claim 1 , wherein
the trench portion includes a first trench portion and a second trench portion and
the floating region is in contact with a bottom portion of the first trench portion.
7. The semiconductor device according to claim 6 , wherein
the drift region is provided between an end of the floating region and the second trench portion in the array direction.
8. The semiconductor device according to claim 6 , wherein
the floating region is also in contact with a bottom portion of the second trench.
9. The semiconductor device according to claim 8 , wherein
the floating region includes an end facing the second trench in the array direction.
10. The semiconductor device according to claim 9 , wherein the floating region includes an end facing the first trench in the array direction.
11. The semiconductor device according to claim 6 , wherein
the first trench portion is a gate trench portion, and the second trench portion is a dummy trench portion.
12. The semiconductor device according to claim 8 , comprising:
an emitter electrode provided above the upper surface of the semiconductor substrate;
an interlayer dielectric film provided between the upper surface of the semiconductor substrate and the emitter electrode; and
a contact hole penetrating the interlayer dielectric film, wherein
the emitter electrode includes: a metal material containing aluminum; a barrier metal provided in a layer below the metal material; and
a plug containing tungsten, provided in the contact hole.
13. The semiconductor device according to claim 12 , wherein
an end of the floating region does not overlap with the contact hole in the array direction, in top view of the semiconductor substrate.
14. The semiconductor device according to claim 12 , wherein
an end of the floating region overlaps with the contact hole in the array direction, in top view of the semiconductor substrate.
15. The semiconductor device according to claim 1 , wherein
the floating region is not continuous with the base region via a second-conductivity-type semiconductor region.
16. The semiconductor device according to claim 6 , comprising:
a transistor section including the first trench portion.
17. The semiconductor device according to claim 16 , comprising:
a diode section including the second trench portion.
18. The semiconductor device according to claim 1 , further comprising:
a second-conductivity-type well region provided over a predetermined area from an end of an active region, and having a lower end that is deeper than the trench portion;
a first electrode provided above the upper surface of the semiconductor substrate;
an interlayer dielectric film provided between the upper surface of the semiconductor substrate and the first electrode; and
a contact hole penetrating the interlayer dielectric film and connecting the mesa portion and the first electrode, wherein
the contact hole extends in the extending direction from a position that is farther from an end of the floating region closest to the well region than the well region to a position that is closer to the well region than the end of the floating region.
19. A semiconductor device comprising:
a semiconductor substrate;
a first-conductivity-type drift region provided in the semiconductor substrate;
a trench portion provided from an upper surface of the semiconductor substrate to an inside of the semiconductor substrate, and extending in a predetermined extending direction in a plane of the upper surface of the semiconductor substrate;
a mesa portion provided in contact with the trench portion in an array direction orthogonal to the extending direction;
a second-conductivity-type base region provided in the mesa portion above the drift region and in contact with the trench portion;
a second-conductivity-type floating region provided in the mesa portion below the base region, in contact with the trench portion, and provided in at least a part of the mesa portion in the array direction; and
a second-conductivity-type well region provided over a predetermined area from an end of an active region, and having a higher doping concentration than the base region; wherein
a distance between the base region and the floating region in a depth direction of the semiconductor substrate is larger than a width of the base region in the depth direction of the semiconductor substrate, and
the floating region is spaced apart from the well region in the extending direction.
20. The semiconductor device according to claim 19 , wherein
the floating region is provided continuously from one side to another side in the extending direction between the well regions.
21. The semiconductor device according to claim 19 , further comprising:
a first electrode provided above the upper surface of the semiconductor substrate;
an interlayer dielectric film provided between the upper surface of the semiconductor substrate and the first electrode; and
a contact hole penetrating the interlayer dielectric film and connecting the mesa portion and the first electrode, wherein
the well region includes a lower end that is deeper than the trench portion, and
the contact hole extends in the extending direction from a position that is farther from an end of the floating region closest to the well region than the well region to a position that is closer to the well region than the end of the floating region.
22. A semiconductor device comprising:
a semiconductor substrate;
a first-conductivity-type drift region provided in the semiconductor substrate;
a trench portion provided from an upper surface of the semiconductor substrate to an inside of the semiconductor substrate, and extending in a predetermined extending direction in a plane of the upper surface of the semiconductor substrate;
a mesa portion provided in contact with the trench portion in an array direction orthogonal to the extending direction;
a second-conductivity-type base region provided in the mesa portion above the drift region and in contact with the trench portion; and
a second-conductivity-type floating region provided in the mesa portion below the base region, in contact with the trench portion, and provided in at least a part of the mesa portion in the array direction, wherein
a distance between the base region and the floating region in a depth direction of the semiconductor substrate is larger than a width of the base region in the depth direction of the semiconductor substrate, and
the floating region is continuous with the base region via a second-conductivity-type semiconductor region.
23. A semiconductor device comprising:
a semiconductor substrate;
a first-conductivity-type drift region provided in the semiconductor substrate;
a trench portion provided from an upper surface of the semiconductor substrate to an inside of the semiconductor substrate, and extending in a predetermined extending direction in a plane of the upper surface of the semiconductor substrate;
a mesa portion provided in contact with the trench portion in an array direction orthogonal to the extending direction;
a second-conductivity-type base region provided in the mesa portion above the drift region and in contact with the trench portion; and
a second-conductivity-type floating region provided in the mesa portion below the base region, in contact with the trench portion, and provided in at least a part of the mesa portion in the array direction, wherein
a distance between the base region and the floating region in a depth direction of the semiconductor substrate is larger than a width of the base region in the depth direction of the semiconductor substrate, and
an end of the floating region overlaps with a contact hole penetrating an interlayer dielectric film in the array direction, in top view of the semiconductor substrate.