Device comprising a chip package and an overlap-free coil layout

1. A device, comprising:

a substrate with an excitation coil configured to generate a first magnetic field in reaction to an input signal fed in, and with a pickup coil arrangement configured to generate an output signal in reaction to a second magnetic field,

wherein the substrate extends in a substrate plane,

wherein the pickup coil arrangement comprises at least one pickup coil configured in one or more metallization layers of the substrate,

wherein the excitation coil comprises one or more turns arranged around the pickup coil arrangement in a ring-shaped manner in a plan view of the substrate plane; and

an electronic chip comprising a circuit configured to feed the excitation coil with the input signal and to detect the output signal of the pickup coil arrangement,

wherein the electronic chip is arranged in a chip package which comprises at least one electrical connection connected to the at least one pickup coil of the pickup coil arrangement by a signal-carrying conductor, and

wherein the chip package is positioned on the substrate in such a way that the signal-carrying conductor and the one or more turns of the excitation coil do not overlap in a plan view of the substrate plane.

2. The device as claimed in claim 1 ,

wherein the chip package is arranged on the substrate in such a way that it extends over at least one of the one or more turns of the excitation coil, in a plan view of the substrate plane, and the at least one turn of the one or more turns the excitation coil thus runs through under the chip package.

3. The device as claimed in claim 1 ,

wherein the one or more turns of the excitation coil comprises 1 to n turns and wherein at least a second to nth turns of the 1 to n turns run through under the chip package.

4. The device as claimed in claim 1 ,

wherein the at least one electrical connection connected to the at least one pickup coil of the pickup coil arrangement is arranged within the excitation coil, in a plan view of the substrate plane.

5. The device as claimed in claim 1 ,

wherein the chip package comprises further electrical connections connected to further pickup coils of the pickup coil arrangement, and

wherein the further electrical connections are arranged within the excitation coil, in a plan view of the substrate plane.

6. The device as claimed in claim 1 ,

wherein a first lateral outer side of the chip package is arranged within the excitation coil, in a plan view of the substrate plane, and

wherein a second lateral outer side of the chip package arranged opposite to the first lateral outer side is arranged outside the excitation coil, in a plan view of the substrate plane.

7. The device as claimed in claim 6 ,

wherein the chip package further comprises two electrical excitation coil connections connected to the excitation coil,

wherein the two electrical excitation coil connections are arranged on the first lateral outer side of the chip package arranged within the excitation coil.

8. The device as claimed in claim 7 ,

wherein the device further comprises an electrical capacitor element connected in parallel with the two electrical excitation coil connections, and

wherein the electrical capacitor element is arranged within the excitation coil, in a plan view of the substrate plane.

9. The device as claimed in claim 6 ,

wherein the chip package further comprises two electrical excitation coil connections connected to the excitation coil,

wherein the two electrical excitation coil connections are arranged on the second lateral outer side of the chip package arranged outside the excitation coil.

10. The device as claimed in claim 9 ,

wherein the device further comprises an electrical resistor element connected in parallel with the two electrical excitation coil connections, and

wherein the electrical resistor element is arranged outside the excitation coil, in a plan view of the substrate plane.

11. The device as claimed in claim 6 ,

wherein the chip package further comprises two electrical excitation coil connections connected to the excitation coil,

wherein a first excitation coil connection of the two electrical excitation coil connections is arranged on the first lateral outer side of the chip package arranged within the excitation coil, and

wherein a second excitation coil connection of the two electrical excitation coil connections is arranged on the second lateral outer side of the chip package arranged outside the excitation coil.

12. The device as claimed in claim 6 ,

wherein the chip package further comprises a power supply connection and also at least one of a signal input connection or a signal output connection,

wherein the power supply connection and the signal input connection or the power supply connection and the signal output connection are arranged on the second lateral outer side of the chip package arranged outside the excitation coil.

13. The device as claimed in claim 1 ,

wherein the device comprises a second pickup coil arrangement,

wherein the one or more turns of the excitation coil are arranged around the second pickup coil arrangement in a ring-shaped manner, in a plan view of the substrate plane, and

wherein the device comprises a second electronic chip for operating the second pickup coil arrangement,

wherein the second electronic chip is arranged in the chip package,

wherein the chip package comprises at least one second electrical connection connected to at least one pickup coil of the second pickup coil arrangement by a second signal-carrying conductor, and

wherein the chip package is positioned on the substrate in such a way that the second signal-carrying conductor and the one or more turns of the excitation coil do not overlap in a plan view of the substrate plane.

14. The device as claimed in claim 1 ,

wherein the chip package is embodied as a leadframeless package, a chip size package, a leadless chip carrier package, a wafer level ball grid array package, or an embedded wafer level ball grid array package.

15. A chip package for a device,

wherein the device comprises

a substrate with an excitation coil configured to generate a first magnetic field in reaction to an input signal fed in, and with a pickup coil arrangement configured to generate an output signal in reaction to a second magnetic field,

wherein the substrate extends in a substrate plane,

wherein the pickup coil arrangement comprises at least one pickup coil configured in one or more metallization layers of the substrate, and

wherein the excitation coil comprises one or more turns arranged around the pickup coil arrangement in a ring-shaped manner in a plan view of the substrate plane; and

an electronic chip comprising a circuit configured to feed the excitation coil with the input signal and to detect the output signal of the pickup coil arrangement,

the chip package comprising:

a housing that houses the electronic chip; and

at least one electrical connection connected to the at least one pickup coil of the pickup coil arrangement by a signal-carrying conductor,

wherein the chip package is positioned on the substrate in such a way that the signal-carrying conductor and the one or more turns of the excitation coil do not overlap in a plan view of the substrate plane.

16. An inductive angle sensor, comprising:

a device comprising:

a substrate with an excitation coil configured to generate a first magnetic field in reaction to an input signal fed in, and with a pickup coil arrangement configured to generate an output signal in reaction to a second magnetic field,

wherein the substrate extends in a substrate plane,

wherein the pickup coil arrangement comprises at least one pickup coil configured in one or more metallization layers of the substrate, and

wherein the excitation coil comprises one or more turns arranged around the pickup coil arrangement in a ring-shaped manner in a plan view of the substrate plane; and

an electronic chip comprising a circuit configured to feed the excitation coil with the input signal and to detect the output signal of the pickup coil arrangement,

wherein the electronic chip is arranged in a chip package which comprises at least one electrical connection connected to the at least one pickup coil of the pickup coil arrangement by a signal-carrying conductor, and

wherein the chip package is positioned on the substrate in such a way that the signal-carrying conductor and the one or more turns of the excitation coil do not overlap in a plan view of the substrate plane.