Integrated circuit with configurable on-die termination
Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, capacitances, or both, which may be controlled using an integrated memory.
1. An integrated-circuit (IC) die comprising:
first and second input pads to receive complementary signals;
a receiver having first and second input nodes coupled respectively to the first and second input pads to receive the complementary signals;
a common node;
a first termination leg to support a first termination topology and a second termination topology, the first termination leg including a first switch in series with a first termination impedance between the first input node of the receiver and the common node;
a second termination leg to support the first termination topology and the second termination topology, the second termination leg including a second switch in series with a second termination impedance between the second input node of the receiver and the common node; and
a third termination leg having capacitors selectively coupled between the common node and a supply node;
wherein the first and second switches are closed in the first termination topology and are open in the second termination topology.
2. The IC die of claim 1 , further comprising a termination resistor extending between the first input pad and the second input pad.
3. The IC die of claim 2 , wherein the termination resistor extends between the first input pad and the second input pad in the second termination topology.
4. The IC die of claim 1 , wherein the supply node is a ground node.
5. The IC die of claim 1 , the third termination leg including a third switch and a third termination impedance connected in series with the capacitors between the common node and the supply node.
6. The IC die of claim 1 , the third termination leg including a third termination impedance connected in series with a third switch and the capacitors between the common node and the supply node.
7. A method of terminating differential first and second input nodes of a receiver on an integrated circuit, the method comprising:
writing a termination setting to a memory, the termination setting indicative of a termination topology for the receiver; and
responsive to the termination setting,
closing a first switch between the first input node and a common node to establish a first termination impedance between the first input node and the common node;
closing a second switch between the second input node and the common node to establish a second termination impedance between the second input node and the common node;
closing a third switch between the common node and a supply node to establish a third termination impedance between the common node and the supply node;
adjusting a resistance in series with the third switch between the common node and the supply node; and
connecting at least one of a plurality of capacitors in series with the third switch and the resistance between the common node and the supply node.
8. The method of claim 7 , further comprising holding the supply node at ground potential.
9. An integrated-circuit (IC) die comprising:
first and second input pads to receive complementary signals;
receiver means for recovering an output signal from the complementary signals;
a first termination leg to support a first termination topology and a second termination topology, the first termination leg including a first switch in series with a first termination impedance between the first input pad and a common node;
a second termination leg to support the first termination topology and the second termination topology, the second termination leg including a second switch in series with a second termination impedance between the second input pad and the common node; and
a third termination leg extending from the common node to a supply node, the third termination leg including parallel capacitors switchably in series with a resistor;
wherein the first and second switches are closed in the first termination topology and are open in the second termination topology.
10. The IC die of claim 9 , further comprising a termination resistor extending between the first input pad and the second input pad.
11. The IC die of claim 10 , wherein the termination resistor extends between the first input pad and the second input pad in the second termination topology.
12. The IC die of claim 9 , the third termination leg including a third switch in series with a third termination impedance and the parallel capacitors.