IP Library › Granted Patent US 11,844,208
Granted Patent B2
US 11,844,208 · App. 17/678,595 · Granted Dec 12, 2023

Semiconductor device and method of forming the same

Inventors: Mitsunari Sukekawa (Hiroshima, JP); Hiroshi Toyama (Sagamihara, JP); Hiroyuki Uno (Chigasaki, JP); Yasutaka Okada (Hiroshima, JP)
Assignee: Micron Technology, Inc.
H10B12/315H10B12/0335H10B12/34H10B12/50
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Quick Facts
Patent No.
US 11,844,208
App. No.
17/678,595
Granted
Dec 12, 2023
Kind
B2
Abstract

An apparatus includes a base structure having a first portion including a plurality of transistors and a second portion surrounding the first portion; a storage structure on the first portion of the base structure, the storage structure including a plurality of storage capacitors each coupled to a corresponding one of the plurality of transistors; an interface structure on the second portion of the base structure; and a peripheral structure on the interface structure; wherein the interface structure is divided into a plurality of insulating films and the plurality of insulating films are arranged away from each other to have a plurality of voids between the second portion of the base structure and the peripheral structure.

Claims (10)

1. An apparatus comprising:

a base structure having a first portion including a plurality of transistors and a second portion surrounding the first portion;

a storage structure on the first portion of the base structure, the storage structure including a plurality of storage capacitors each coupled to a corresponding one of the plurality of transistors;

an interface structure on the second portion of the base structure; and

a peripheral structure on the interface structure;

wherein the interface structure is divided into a plurality of insulating films and the plurality of insulating films are arranged away from each other to have a plurality of voids between the second portion of the base structure and the peripheral structure.

2. The apparatus of claim 1 , wherein the interface structure comprises dielectric material.

3. The apparatus of claim 1 , wherein each void of the plurality of voids is surrounded by dielectric material, respectively.

4. The apparatus of claim 1 , wherein each void of the plurality of voids is arranged so as to be between the storage structure and the base structure, respectively.

5. The apparatus of claim 1 , wherein each of the storage capacitors comprises a first conductive film, a second conductive film, and a high-K film between the first conductive film and the second conductive film, respectively.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2022
From: SUKEKAWA, MITSUNARI; TOYAMA, HIROSHI; UNO, HIROYUKI; OKADA, YASUTAKA
To: MICRON TECHNOLOGY, INC.
Reel/Frame 059079/0397 →
Continuity (1)
Related Publication 20230269932A1 · Aug 24, 2023
Cited By (1)
US 12,490,442