Semiconductor device package comprising power module and passive elements
A semiconductor device package is provided. The semiconductor device package includes providing a first substrate, a computing unit and a power module. The first substrate has a first surface and a second surface opposite to the first surface. The computing unit is adjacent to the first surface. The computing unit includes a semiconductor die. The power module is adjacent to the second surface. The power module includes a power element and a passive element. Each of the semiconductor die, the power element, and the passive element is vertically arranged with respect to each other, and the passive elements are assembled between the semiconductor die and the power element.
1. A semiconductor device package, comprising:
a first substrate having a first surface and a second surface opposite to the first surface,
a first passive element disposed on the first substrate;
a second substrate having a third surface and a fourth surface opposite to the third surface, the third surface facing the second surface of the first substrate,
a power element being adjacent to the fourth surface;
a via embedded in the second substrate and disposed between the first passive element and the power element; and
a die adjacent to the first surface of the first substrate, wherein a projection of the die, a projection of the first passive element, and a projection of the power element on the first substrate overlap each other.
2. The semiconductor device package of claim 1 , wherein the power element is disposed on the fourth surface of the second substrate.
3. The semiconductor device package of claim 1 , wherein the first passive element is disposed between the die and the power element.
4. The semiconductor device package of claim 1 , further comprising:
a conductive terminal disposed between and electrically connecting the first substrate and the second substrate.
5. The semiconductor device package of claim 1 , further comprising:
a second passive element disposed on the fourth surface of the second substrate and electrically connected to the power element.
6. The semiconductor device package of claim 5 , wherein the second passive element comprises an inductor stacked with the power element.