IP Library › Granted Patent US 11,848,676

Granted Patent B2

US 11,848,676 · App. 17/181,869 · Granted Dec 19, 2023

Interference reducing passive transmission line receiver

Inventor: Stephen Whiteley (Sunnyvale, CA)

Assignee: Synopsys, Inc.

H03K3/38 G06N10/00 H03K17/92 G01R33/035 H03K19/195 H03K19/1954 H10N60/12

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Quick Facts

Patent No.: US 11,848,676
App. No.: 17/181,869
Granted: Dec 19, 2023
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

The present disclosure relates to improved electronic structures for propagating logic states between superconducting digital logic gates using a three-junction interferometer in a receiver circuit to reduce reflecting signals that otherwise result in distortions in the signals being transmitted between the gates. Other improved electronic structures comprise passive transmission lines (PTLs) with transmission line matching circuitry that has previously been avoided. The matching circuitry minimizes generation and propagation of spurious pulses emitted by Josephson junctions used in the digital logic gates.

Claims (50)

1. A three-junction interferometer, including:

an input port;

a reference potential terminal;

a first Josephson junction having a first and second terminal, the first terminal coupled to the input port;

a second Josephson junction having a first and second terminal, the first terminal of the second Josephson junction being coupled to the second terminal of the first Josephson junction and the second terminal of the second Josephson junction being coupled to the reference potential terminal;

a first inductance having a first and second terminal, the first terminal of the first inductance being coupled to the second terminal of the first Josephson junction; and

a third Josephson junction having a first and second terminal, the first terminal of the third Josephson junction being coupled to the second terminal of the first inductance and the second terminal of the third Josephson junction being coupled to the reference potential terminal.

2. The three-junction interferometer of claim 1 , further comprising a second inductance having a first and second terminal, the first terminal of the second inductance coupled to the first terminal of the first Josephson junction and the second terminal of the second inductance coupled to the reference potential terminal.

3. The three-junction interferometer of claim 2 , further comprising an impedance matching device having a first and second terminal, the first terminal coupled to the input port and the second terminal configured to receive signals from a transmission line having a characteristic impedance, wherein the impedance of the impedance matching device is matched to the characteristic impedance of the transmission line.

4. The three-junction interferometer of claim 1 , further comprising a first current source having a current in port and a current out port, the current in port coupled to the reference potential terminal and the current out port coupled to the first terminal of the second Josephson junction.

5. The three-junction interferometer of claim 4 , further comprising a second current source having a current in port and a current out port, the current in port of the second current source coupled to the reference potential terminal and the current out port of the second current source coupled to the first terminal of the third Josephson junction.

6. The three-junction interferometer of claim 1 , further comprising an impedance matching device having a first and second terminal, the first terminal coupled to the input port and the second terminal configured to receive signals from a transmission line having a characteristic impedance, wherein the impedance of the impedance matching device is matched to the characteristic impedance of the transmission line.

7. A three-junction interferometer, including:

(a) an input port;

(b) a reference potential terminal;

(d) a second Josephson junction having a first and second terminal, the first terminal coupled to the second terminal of the first Josephson junction and the second terminal coupled to the reference potential terminal;

(e) a first inductance having a first and second terminal, the first terminal coupled to the second terminal of the first Josephson junction;

(f) a first current source having a current in port and a current out port, the current in port coupled to the second terminal of the second inductance;

(g) a second inductance having a first and second terminal, the first terminal of the second inductance coupled to the first terminal of the current out port of the first current source;

(h) a third Josephson junction having a first and second terminal, the first terminal coupled to the second terminal of the second inductance and the second terminal coupled to the reference potential terminal.

8. The three-junction interferometer of claim 7 , further comprising a second current source having a current in port and a current out port, the current in port coupled to the reference potential terminal and the current out port coupled to the second terminal of the first Josephson junction.

9. The three-junction interferometer of claim 7 , further comprising an impedance matching device having a first and second terminal, the first terminal of the impedance matching device coupled to the input of the three-junction interferometer and the second terminal of the impedance matching device configured to receive an input signal.

10. A digital logic circuit comprising:

(a) a driver circuit configured to receive a single flux quantum (SFQ) input signal and convert the SFQ input signal into a non-SFQ voltage, the driver circuit comprising:

(1) a first inductance having a first and second terminal;

(2) a second inductance having a first and second terminal, the first terminal of the second inductance coupled to the second terminal of the first inductance;

(3) a drive resistance having a first and second terminal, the first terminal of the drive resistance coupled to the second terminal of the second inductance;

(4) a first Josephson junction having a first and second terminal, the first terminal of the first Josephson junction coupled to the second terminal of the first inductance, the second terminal of the first Josephson junction coupled to a reference potential; and

(5) a second Josephson junction having a first and second terminal, the first terminal of the second Josephson junction coupled to the second terminal of the second inductance, the second terminal of the second Josephson junction coupled to a reference potential;

(b) a passive transmission line (PTL) having a driver end and a receiver end, the receiver end coupled to the second terminal of the drive resistance and having an impedance that is matched to the impedance of the drive resistance; and

(1) a third Josephson junction having a first and second terminal, the first terminal of the third Josephson junction coupled to the receiver end of the PTL and the second terminal of the third Josephson junction coupled to the reference potential.

11. The digital logic circuit of claim 10 , wherein the driver circuit further comprises:

(a) a first current source having a current in port and a current out port, the current in port of the first current source coupled to a reference potential, the current out port of the first current source coupled to the first terminal of the first Josephson junction;

(b) a second current source having a current in port and a current out port, the current in port of the second current source coupled to a reference potential, the current out port of the second current source coupled to the first terminal of the second Josephson junction; and

wherein the receiver further comprises:

(a) a third current source having a current in port and a current out port, the current in port of the third current source coupled to a reference potential, the current out port of the third current source coupled to the first terminal of the third Josephson junction.

12. The digital logic circuit of claim 10 , the receiver further comprising:

(a) a fourth Josephson junction having a first and second terminal, the first terminal of the fourth Josephson junction coupled to the second terminal of the drive resistance and the second terminal of the fourth Josephson junction coupled to the first terminal of the first Josephson junction, such that the fourth Josephson junction is interposed between the second terminal of the drive resistance and the first terminal of the third Josephson junction;

(b) a third inductance having a first and second terminal, the first terminal of the third inductance coupled to the first terminal of the fourth Josephson junction and the second terminal of the third inductance coupled to the reference potential;

(c) a fourth inductance having a first and second terminal, the first terminal coupled to the second terminal of the fourth Josephson junction; and

(d) a fifth Josephson junction having a first and second terminal, the first terminal of the fifth Josephson junction coupled to the second terminal of the fourth inductance and the second terminal of the fifth Josephson junction coupled to the reference potential.

13. The digital logic circuit of claim 12 , wherein the driver circuit further comprises:

wherein the receiver further comprises:

(b) a fourth current source having a current in port and a current out port, the current in port coupled to the reference potential and the current out port coupled to the second terminal of the fourth inductance.

14. The digital logic circuit of claim 13 , wherein the drive resistance and the PTL have an impedance of 16 Ohms.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2021

From: WHITELEY, STEPHEN

To: SYNOPSYS, INC.

Reel/Frame 055357/0847 →

Continuity (2)

Provisional Application 62983392 · Feb 28, 2020

Related Publication 20230145418A1 · May 11, 2023

Cited By (1)

US 12,320,848