Power rails for stacked semiconductor device

1. A method, comprising:

forming, on a first surface of a substrate, a first device having a first source/drain (S/D) region stacked over a second device having a second S/D region;

etching a second surface of the substrate and a portion of the first S/D region to form a first opening, wherein the second surface is opposite to the first surface;

forming, in the first opening, a first S/D contact structure in contact with the first S/D region;

etching the second surface of the substrate and a portion of the second S/D region to form a second opening; and

forming, in the second opening, a second S/D contact structure in contact with the second S/D region.

2. The method of claim 1 , further comprising:

replacing the substrate with a dielectric layer;

forming a first interconnect connected to the first S/D contact structure and a second interconnect connected to the second S/D contact structure; and

connecting the first interconnect to a power supply and the second interconnect to ground.

3. The method of claim 2 , wherein the replacing the substrate comprises:

removing the substrate; and

forming the dielectric layer over the first and second devices, wherein the dielectric layer comprises silicon oxide.

4. The method of claim 1 , further comprising:

forming a bonding layer on the first surface of the substrate;

bonding an additional substrate to the bonding layer;

flipping the substrate on top of the additional substrate; and

removing a portion of the substrate.

5. The method of claim 1 , further comprising:

depositing a dielectric layer in the first opening;

removing a portion of the dielectric layer on the first S/D region; and

forming the first S/D contact structure on the dielectric layer.

6. The method of claim 1 , wherein the forming the first S/D contact structure comprises:

forming a silicide layer on the first S/D region; and

forming a metal contact structure on the silicide layer.

7. The method of claim 1 , wherein:

the portion of the first S/D region comprises a first epitaxial stop layer and the portion of the second S/D region comprises a second epitaxial stop layer; and

the first device comprises a plurality of semiconductor layers and a gate dielectric layer having a negative capacitance dielectric material.

8. The method of claim 1 , further comprising forming an isolation structure between the first and second devices.

9. A method, comprising:

forming, on a first surface of a substrate, a cross-over stacked semiconductor device including a first device stacked over a second device, wherein the cross-over stacked semiconductor device comprises a source/drain (S/D) region;

etching a second surface of the substrate and a portion of the S/D region to form an opening, wherein the second surface is opposite to the first surface; and

forming, in the opening, a S/D contact structure in contact with the S/D region.

10. The method of claim 9 , further comprising:

replacing the substrate with a dielectric layer;

forming, in the dielectric layer, an interconnect connected to the S/D contact structure; and

connecting the interconnect to a power supply.

11. The method of claim 10 , wherein the replacing the substrate comprises:

removing the substrate; and

forming the dielectric layer on the cross-over stacked semiconductor device, wherein the dielectric layer comprises silicon oxide.

12. The method of claim 9 , further comprising:

replacing the substrate with a dielectric layer;

forming, in the dielectric layer, an interconnect connected to the S/D contact structure; and

connecting the interconnect to ground.

13. The method of claim 9 , further comprising:

forming a bonding layer on the first surface of the substrate;

bonding an additional substrate to the bonding layer;

flipping the substrate on top of the additional substrate; and

removing a portion of the substrate.

14. The method of claim 9 , further comprising:

depositing a dielectric layer in the opening;

removing a portion of the dielectric layer on the S/D region; and

forming the S/D contact structure on the dielectric layer.

15. The method of claim 9 , wherein the forming the S/D contact structure comprises:

forming a silicide layer on the S/D region; and

forming a metal contact structure on the silicide layer.

16. The method of claim 9 , wherein:

the portion of the S/D region comprises an epitaxial stop layer; and

the cross-over stacked semiconductor device further comprises a plurality of semiconductor layers and a gate dielectric layer having a negative capacitance dielectric material.

17. A method, comprising:

forming, on a first surface of a substrate, a first device having a first source/drain (S/D) region stacked over a second device having a second S/D region, wherein the first source/drain region is connected to a first S/D contact on the first surface;

etching a second surface of the substrate and a portion of the second S/D region to form an opening, wherein the second surface is opposite to the first surface; and

forming, in the opening, a second S/D contact structure in contact with the first S/D region.

18. The method of claim 17 , further comprising:

forming an interconnect connected to the second S/D contact structure; and

connecting the interconnect to a power supply.

19. The method of claim 17 , further comprising:

forming a bonding layer on the first surface of the substrate;

bonding an additional substrate to the bonding layer;

flipping the substrate on top of the additional substrate; and

removing a portion of the substrate.

20. The method of claim 17 , further comprising:

depositing a dielectric layer in the opening;

removing a portion of the dielectric layer on the second S/D region;

forming a silicide layer on the second S/D region; and

forming a metal contact structure on the silicide layer.