Semiconductor packages and methods for forming the same
View Patent ↗Embodiments of the present disclosure provide a stacking edge interconnect chiplet. In one embodiment, a semiconductor device is provided. The semiconductor device includes a first integrated circuit die comprising a first device layer having a first side and a second side opposite the first side, a first interconnect structure disposed on the first side of the first device layer, and a second interconnect structure disposed on the second side of the first device layer. The semiconductor device also includes a power line extending through the first device layer and in contact with the first interconnect structure and the second interconnect structure, and a second integrated circuit die disposed over the first integrated circuit die, the second integrated circuit die comprising a third interconnect structure in contact with the second interconnect structure of the first integrated circuit die.
1. A method for forming a semiconductor package, comprising:
forming a first integrated circuit die having a first circuit design on a substrate;
forming a second integrated circuit die having a second circuit design on the substrate;
forming a first interconnect structure on a first surface of the first integrated circuit die;
forming a second interconnect structure on a first surface of the second integrated circuit die;
forming an edge interconnect feature having a first end in contact with the first interconnect structure and a second end in contact with the second interconnect structure;
forming one or more power rails on a second surface of the first and second integrated circuit dies, respectively;
forming a third interconnect structure on the second surface of the first integrated circuit die, the third interconnect structure being in contact with the one or more power rails;
forming a fourth interconnect structure on the second surface of the second integrated circuit die, the fourth interconnect structure being in contact with the one or more power rails;
forming a third integrated circuit die having a third circuit design;
forming a fifth interconnect structure on the third integrated circuit die;
bonding the fifth interconnect structure to the third and fourth interconnect structures; and
attaching the first and second interconnect structures to a redistribution layer.
2. The method of claim 1 , further comprising:
forming a first power line in the first integrated circuit die, the first power line extending between and in contact with the first interconnect structure and the third interconnect structure.
3. The method of claim 2 , further comprising:
forming a fourth integrated circuit die adjacent the first integrated circuit die, the fourth integrated circuit die having a sixth interconnect structure in contact with the redistribution layer.
4. The method of claim 2 , further comprising:
forming a second power line in the second integrated circuit die, the second power line extending between and in contact with the second interconnect structure and the fourth interconnect structure.
5. The method of claim 1 , further comprising:
separating the first integrated circuit die and the second integrated circuit die by a scribe line.
6. The method of claim 5 , wherein forming an edge interconnect feature comprises extending a portion of the edge interconnect feature through the scribe line.
7. The method of claim 6 , wherein the first end of the edge interconnect feature is operable to be electrically connected to one or more conductive features in the first interconnect structure, and the second end of the edge interconnect feature is operable to be electrically connected to one or more conductive features in the second interconnect structure.
8. The method of claim 6 , wherein a portion of the edge interconnect feature is formed in an intermetal dielectric (IMD) layer.
9. The method of claim 8 , wherein the first end of the edge interconnect feature is electrically connected to one or more conductive features in the first interconnect structure, and the second end of the edge interconnect feature is floating in the IMD layer without electrically connected to conductive features in the second interconnect structure.