Semiconductor interconnection structure and methods of forming the same
An interconnect structure includes a dielectric layer, a first conductive feature, a hard mask layer, a conductive layer, and a capping layer. The first conductive feature is disposed in the dielectric layer. The hard mask layer is disposed on the first conductive feature. The conductive layer includes a first portion and a second portion, the first portion of the conductive layer is disposed over at least a first portion of the hard mask layer, and the second portion of the conductive layer is disposed over the dielectric layer. The hard mask layer and the conductive layer are formed by different materials. The capping layer is disposed on the dielectric layer and the conductive layer.
1. An interconnection structure, comprising:
a dielectric layer;
a first conductive feature disposed in the dielectric layer;
a hard mask layer disposed on the first conductive feature;
a conductive layer comprising a first portion and a second portion, wherein the first portion of the conductive layer is disposed over at least a first portion of the hard mask layer, and the second portion of the conductive layer is disposed over the dielectric layer, and wherein the hard mask layer and the conductive layer are formed by different materials;
a capping layer disposed on the dielectric layer and the conductive layer;
a dielectric fill disposed over the capping layer between the first portion and the second portion of the conductive layer;
an etch stop layer disposed over the dielectric fill and the conductive layer;
a dielectric material disposed over the etch stop layer; and
a second conductive feature disposed in the dielectric material over the first portion of the conductive layer.
2. The interconnection structure of claim 1 , wherein the capping layer is further disposed on a second portion of the hard mask layer different from the first portion of the hard mask layer.
3. The interconnection structure of claim 1 , wherein the capping layer is further disposed on a portion of the first conductive feature.
4. The interconnection structure of claim 1 , wherein an air gap is formed in the dielectric fill between the first portion and the second portion of the conductive layer.
5. A method for forming an interconnection structure, comprising:
forming a first conductive feature in a dielectric layer;
forming a blocking layer on the dielectric layer;
forming a hard mask layer on the first conductive feature;
removing the blocking layer;
forming a conductive layer over the dielectric layer and the hard mask layer,
wherein the hard mask layer and the conductive layer are formed by different materials;
forming one or more openings in the conductive layer to expose portions of dielectric surface of the dielectric layer; and
forming a capping layer on exposed portions of the dielectric surface of the dielectric layer and conductive surface of the conductive layer.
6. The method of claim 5 , wherein forming the blocking layer on the dielectric layer, comprises:
performing an oxide inhibition process to form the blocking layer on the dielectric layer.
7. The method of claim 6 , wherein a silane based self-assembled monolayer (SAM) is used as an inhibitor in the oxide inhibition process.
8. The method of claim 6 , wherein the blocking layer comprises a polymer formed by silicon (Si), carbon (C), nitrogen (N) or oxygen (O).
9. The method of claim 5 , wherein the hard mask layer comprises a tantalum nitride (TaN) layer.
10. The method of claim 5 , wherein forming one or more openings in the conductive layer to expose portions of dielectric surface of the dielectric layer, comprises:
performing a first etch process to remove a portion of the conductive layer to expose portions of dielectric surface of the dielectric layer.
11. The method of claim 5 , wherein forming one or more openings in the conductive layer to expose portions of dielectric surface of the dielectric layer, comprises:
performing a first etch process to remove a portion of the conductive layer to expose portions of dielectric surface of the dielectric layer and a portion of the hard mask layer, wherein the hard mask layer and the conductive layer have different etch selectivity in the first etch process.
12. The method of claim 11 , wherein forming the capping layer on exposed portions of the dielectric surface of the dielectric layer and conductive surface of the conductive layer, comprises:
forming the capping layer on exposed portions of the dielectric surface of the dielectric layer, conductive surface of the conductive layer, and the exposed portion of the hard mask layer.
13. The method of claim 5 , wherein forming one or more openings in the conductive layer to expose portions of dielectric surface of the dielectric layer, comprises:
performing a first etch process to remove a portion of the conductive layer to expose portions of dielectric surface of the dielectric layer and a portion of the hard mask layer; and
performing a second etch process to remove the exposed portion of the hard mask layer to expose a portion of the first conductive feature.
14. The method of claim 13 , wherein forming the capping layer on exposed portions of the dielectric surface of the dielectric layer and conductive surface of the conductive layer, comprises:
forming the capping layer on exposed portions of the dielectric surface of the dielectric layer, conductive surface of the conductive layer, and the exposed portion of the first conductive feature.
15. The method of claim 5 further comprising:
forming a sacrificial layer in the one or more openings;
recessing the sacrificial layer;
forming a support layer on the recessed sacrificial layer in each of the one or more openings;
removing the sacrificial layer to form an air gap in each of the one or more openings;
forming a dielectric fill on the support layer; and
performing a planarization process to remove a portion of the dielectric fill and a portion of the capping layer to expose portions of the conductive layer.
16. The method of claim 15 further comprising:
forming an etch stop layer over the dielectric fill and the exposed portions of the conductive layer;
forming a dielectric material over the etch stop layer; and
forming a second conductive feature in the dielectric material over the conductive layer.
17. A method for forming an interconnection structure, comprising:
forming a first conductive feature in a dielectric layer;
forming a hard mask layer on the first conductive feature;
forming a second conductive feature over a portion of the dielectric layer and a first portion of the hard mask layer, wherein the hard mask layer and the second conductive feature are formed by different materials;
converting a second portion of the hard mask layer to a different material;
removing the second portion of the hard mask layer to expose a portion of the first conductive feature; and
forming a capping layer on the dielectric layer, the second conductive feature and the exposed portion of the first conductive feature.
18. The method of claim 17 further comprising:
forming a dielectric fill over the capping layer;
performing a planarization process to remove a portion of the dielectric fill and a portion of the capping layer and expose a portion of the second conductive feature;
forming an etch stop layer over the dielectric fill and the exposed second conductive feature;
forming a dielectric material over the etch stop layer; and
forming a third conductive feature in the dielectric material in contact with the second conductive feature.
19. The method of claim 18 , wherein the dielectric fill comprises an air gap.
20. The method of claim 17 , wherein the hard mask layer comprises a metal nitride, and the second portion of the hard mask layer is converted to a metal oxide.