Three-dimensional device structure including substrate-embedded integrated passive device and methods for making the same
A three-dimensional device structure includes a die including a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate, a through silicon via (TSV) structure that extends through the semiconductor substrate and electrically contacts a metal feature of the interconnect structure, and an integrated passive device (IPD) embedded in the semiconductor substrate and electrically connected to the TSV structure.
1. A three-dimensional device structure comprising a die, wherein the die comprises:
a semiconductor substrate;
an interconnect structure disposed on the semiconductor substrate;
a through silicon via (TSV) structure that extends through the semiconductor substrate and electrically contacts a metal feature of the interconnect structure; and
an integrated passive device (IPD) embedded in the semiconductor substrate and electrically connected to the TSV structure, wherein the IPD comprises a deep trench capacitor (DTC) disposed in a trench formed in the semiconductor substrate.
2. The three-dimensional device structure of claim 1 , wherein the DTC comprises:
a first conductive layer electrically connected to the TSV structure;
a second conductive layer electrically connected to a metal feature a front side bonding layer; and
a first dielectric layer disposed between the first conductive layer and the second conductive layer.
3. The three-dimensional device structure of claim 2 , wherein the second conductive layer surrounds the second dielectric layer.
4. The three-dimensional device structure of claim 1 , wherein the DTC is configured to provide power to transistors of the semiconductor substrate.
5. A three-dimensional device structure comprising:
a first die comprising a first semiconductor substrate;
a second die bonded to the first die and comprising a second semiconductor substrate and a through silicon via (TSV) structure that extends through the second semiconductor substrate; and
an integrated passive device (IPD) embedded in the second semiconductor substrate and electrically connected to the TSV structure, wherein the IPD comprises a deep trench capacitor (DTC) disposed in a trench formed in the second semiconductor substrate.
6. The three-dimensional device structure of claim 5 , wherein the DTC comprises:
a first conductive layer electrically connected to the TSV structure;
a second conductive layer electrically connected to a metal feature a front side bonding layer; and
a first dielectric layer disposed between the first conductive layer and the second conductive layer.
7. The three-dimensional device structure of claim 6 , wherein the second conductive layer surrounds the second dielectric layer.
8. The three-dimensional device structure of claim 6 , wherein:
the second die comprises a second interconnect structure configured to electrically connect the second die to the first die; and
the TSV structure is electrically connected to metal features of the second interconnect structure.
9. The three-dimensional device structure of claim 6 , further comprising a third die bonded to the second die and comprising a third semiconductor substrate and a third interconnect structure,
wherein the second conductive layer of the DTC is electrically connected to metal features of the third interconnect structure.
10. The three-dimensional device structure of claim 9 , further comprising a redistribution layer structure disposed over the third die,
wherein the third die comprises a TSV structure that electrically connects the metal features of the third interconnect structure to metal features of the redistribution layer structure.
11. The three-dimensional device structure of claim 9 , wherein the DTC is configured to provide power to electrical components of the first semiconductor substrate, the second semiconductor substrate, or the third semiconductor substrate.
12. The three-dimensional device structure of claim 6 , wherein:
the DTC comprises a contact flange comprising end regions of the first conductive layer, first dielectric layer, and the second conductive layer that are disposed on an upper surface of the second semiconductor substrate; and
the TSV structure electrically contacts the contact flange.
13. The three-dimensional device structure of claim 5 , wherein the IPD comprises deep trench capacitors (DTCs) disposed in trenches formed in the second semiconductor substrate.
14. The three-dimensional device structure of claim 5 , further comprising a deep trench capacitor (DTC) disposed in a trench formed in the first semiconductor substrate.
15. The three-dimensional device structure of claim 5 , further comprising a wafer bonded to the first die.
16. A three-dimensional device structure comprising:
a first die comprising a first semiconductor substrate;
a second die bonded to the first die and comprising a second semiconductor substrate and a through silicon via (TSV) structure that extends through the second semiconductor substrate;
a deep trench capacitor (DTC) embedded in the second semiconductor substrate and electrically connected to the TSV structure;
a third die bonded to the second die and comprising a third semiconductor substrate; and
a redistribution layer structure disposed over the third die.
17. The three-dimensional device structure of claim 8 , further comprising:
a plurality of TSV structures extending through the second semiconductor substrate; and
a plurality of DTCs embedded in the second semiconductor substrate and connected to the plurality of TSV structures.