Physical unclonable function (PUF) security key generation
Systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (PUF) generator. Unstable bits of the plurality of key bits are identified, and a security key is generated based on the plurality of key bits, wherein the security key excludes the identified unstable bits.
1. A method for generating a security key, comprising:
generating a first occurrence of a first key bit;
generating a second occurrence of the first key bit;
comparing the first and second occurrences of the first key bit to identify an unstable key bit; and
storing the identified unstable key bit in a memory, wherein the memory does not store stable key bits.
2. The method of claim 1 , further comprising generating the first and second occurrences of the first key bit under a first test condition.
3. The method of claim 2 , further comprising:
generating a third occurrence of the security key under a second test condition;
generating a fourth occurrence of the security key under the second test condition; and
comparing the key bits of the third and fourth occurrences of the security key.
4. The method of claim 1 , further comprising:
generating a third occurrence of the first key bit;
comparing the second and third occurrences of the first key bit to identify a second unstable key bit; and
storing the second identified unstable key bit in the memory.
5. A method of generating a security key for an integrated circuit device, comprising:
providing a plurality of memory cells;
comparing access speeds of the plurality of memory cells;
generating a plurality of key bits based on the compared access speeds;
identifying at least one unstable bit of the plurality of key bits; and
generating a security key based on the plurality of key bits, wherein the security key excludes the at least one unstable bit.
6. The method claim 5 , further comprising saving addresses of the unstable bits in a memory.
7. The method claim 6 , wherein the memory does not store stable bits of the plurality of key bits.
8. The method of claim 6 , wherein the memory is located on the integrated circuit device.
9. The method of claim 6 , wherein the memory is located external to the integrated circuit device.
10. The method of claim 5 , wherein the generating the plurality of key bits includes writing a predetermined data bit to each of the memory cells, and comparing read speeds of the two of the plurality of memory cells to each other.
11. The method claim 5 , further comprising receiving a challenge address, and wherein the security key is generated further in response to the received challenge address.
12. The method claim 11 , wherein the security key further includes an error correction code.
13. The method claim 1 , wherein identifying the at least one unstable bit comprises:
generating a first occurrence of the security key under a first test condition;
generating a second occurrence of the security key under the first test condition; and
comparing the key bits of the first and second occurrences of the security key.
14. The method of claim 13 , further comprising:
generating a third occurrence of the security key under a second test condition;
generating a fourth occurrence of the security key under the second test condition; and
comparing the key bits of the third and fourth occurrences of the security key.
15. The method claim 5 , further comprising:
generating a plurality of security keys that includes the security key;
determining a plurality of challenge addresses corresponding to the plurality of security keys; and
storing the plurality of security keys and associated challenge addresses in a database.
16. A device, comprising:
a plurality of memory cells;
a PUF generator configured to:
compare access speeds of the plurality of memory cells to each other;
generate a plurality of key bits based on the comparisons;
identify at least one unstable bit of the plurality of key bits;
generate a security key based on the plurality of key bits, wherein the security key excludes the at least one unstable bit; and
a memory accessible by the PUF generator and configured to store the unstable bit.
17. The integrated circuit device of claim 16 , wherein:
the plurality of memory cells includes a first memory cell and a second memory cell;
the PUF generator is configured to compare an access speed of the first memory cell to an access speed of the second memory cell, and generate a key bit based on the comparison.
18. The integrated circuit device of claim 16 , further comprising a controller configured to generate a security key in response to receiving a challenge, wherein generating the security key includes accessing the memory and excluding the unstable bits from the security key.
19. The integrated circuit device of claim 16 , wherein the memory is external to the integrated circuit device.
20. The integrated circuit device of claim 16 , wherein the memory comprises a nonvolatile memory.