Organic light emitting diode display
An organic light emitting diode display according to an exemplary embodiment includes: a substrate; a first buffer layer on the substrate; a first semiconductor layer on the first buffer layer; a first gate insulating layer on the first semiconductor layer; a first gate electrode and a blocking layer on the first gate insulating layer; a second buffer layer on the first gate electrode; a second semiconductor layer on the second buffer layer; a second gate insulating layer on the second semiconductor layer; and a second gate electrode on the second gate insulating layer.
1. An organic light emitting diode display, comprising:
a substrate;
a first buffer layer on the substrate;
a first semiconductor layer on the first buffer layer;
a first gate insulating layer on the first semiconductor layer;
a first gate electrode on the first gate insulating layer;
a second gate insulating layer on the first gate electrode;
a second gate electrode and a blocking layer on the second gate insulating layer;
a second buffer layer on the second gate electrode and the blocking layer;
a second semiconductor layer on the second buffer layer, the second semiconductor layer including a channel region;
a third gate insulating layer on the second semiconductor layer; and
a third gate electrode on the third gate insulating layer, wherein
the blocking layer is disposed in a same layer as the second gate electrode, the blocking layer overlapping the channel region of the second semiconductor layer in a direction perpendicular to a surface of the substrate.
2. The organic light emitting diode display as claimed in claim 1 , further comprising:
an interlayer insulating layer on the third gate electrode;
a first electrode and a second electrode on the interlayer insulating layer, wherein
the first electrode is in contact with the first semiconductor layer, and
the second electrode is in contact with the second semiconductor layer.
3. The organic light emitting diode display as claimed in claim 2 , wherein
the first electrode and the second electrode are in contact with a top surface of the interlayer insulating layer.
4. The organic light emitting diode display as claimed in claim 3 , further comprising:
a driving voltage line transmitting a driving voltage, wherein
the blocking layer is electrically connected to the driving voltage line.
5. The organic light emitting diode display as claimed in claim 2 , wherein
the second gate electrode overlaps the first gate electrode in a direction perpendicular to the surface of the substrate.
6. The organic light emitting diode display as claimed in claim 2 , further comprising:
a passivation layer on the first electrode and the second electrode;
a pixel electrode on the passivation layer;
an organic emission layer on the pixel electrode; and
a common electrode on the organic emission layer.
7. The organic light emitting diode display as claimed in claim 6 , wherein
the pixel electrode is electrically connected to the second electrode.
8. The organic light emitting diode display as claimed in claim 7 , further comprising:
an encapsulation layer on the common electrode.
9. The organic light emitting diode display as claimed in claim 1 , wherein
one of the first semiconductor layer and the second semiconductor layer is an oxide semiconductor and the other includes polysilicon.
10. The organic light emitting diode display as claimed in claim 1 , wherein the blocking layer does not overlap the second gate electrode in a direction perpendicular to the surface of the substrate.
11. The organic light emitting diode display of claim 1 , further comprising a driving voltage line transmitting a driving voltage, wherein the blocking layer is electrically connected to the driving voltage line.
12. The organic light emitting diode display of claim 11 , further comprising an interlayer insulating layer disposed on the third gate electrode, wherein the driving voltage line is disposed on the interlayer insulating layer.
13. The organic light emitting display device of claim 1 , wherein the blocking layer is comprised of a metal having a conductive characteristic.
14. The organic light emitting display device of claim 1 , wherein the blocking layer to minimize a kickback voltage due to parasitic capacitance of a first transistor and a second transistor, wherein the first transistor comprises the first semiconductor layer and the first gate electrode and the second transistor comprises the second semiconductor layer and the third gate electrode.
15. The organic light emitting display device of claim 1 , wherein the blocking layer is connected to a driving voltage line to receive a driving voltage to prevent deterioration of display quality due to unnecessary parasitic capacitance of a first transistor that comprises the first semiconductor layer and of a second transistor that comprises the second semiconductor layer.
16. An organic light emitting diode display, comprising:
a substrate;
a first buffer layer on the substrate;
a first semiconductor layer on the first buffer layer;
a first gate insulating layer on the first semiconductor layer;
a first gate electrode on the first gate insulating layer;
a second gate insulating layer on the first gate electrode;
a second gate electrode and a blocking layer on the second gate insulating layer;
a second buffer layer on the second gate electrode and the blocking layer;
a second semiconductor layer on the second buffer layer, the second semiconductor layer including a channel region;
a third gate insulating layer on the second semiconductor layer; and
a third gate electrode on the third gate insulating layer, wherein the blocking layer is disposed in a same layer as the second gate electrode, the blocking layer overlapping the channel region of the second semiconductor layer in a direction perpendicular to a surface of the substrate, wherein the blocking layer comprises a same material as the second gate electrode.
17. An organic light emitting diode display, comprising:
a substrate;
a first buffer layer on the substrate;
a first semiconductor layer on the first buffer layer;
a first gate insulating layer on the first semiconductor layer;
a first gate electrode on the first gate insulating layer;
a second gate insulating layer on the first gate electrode;
a second gate electrode and a blocking layer on the second gate insulating layer;
a second buffer layer on the second gate electrode and the blocking layer;
a second semiconductor layer on the second buffer layer, the second semiconductor layer including a channel region;
a third gate insulating layer on the second semiconductor layer; and
a third gate electrode on the third gate insulating layer, wherein
the blocking layer is disposed in a same layer as the second gate electrode, the blocking layer overlapping the channel region of the second semiconductor layer in a direction perpendicular to a surface of the substrate, wherein the blocking layer is electrically conductive.