Macro-op fusion
Systems and methods are disclosed for macro-op fusion. Sequences of macro-ops that include a control-flow instruction are fused into single micro-ops for execution. The fused micro-ops may avoid the use of control-flow instructions, which may improve performance. A fusion predictor may be used to facilitate macro-op fusion.
1. An integrated circuit for executing instructions comprising:
one or more execution resource circuits configured to execute micro-ops to support an instruction set including macro-ops,
an instruction decode buffer configured to store macro-ops fetched from memory, and
an instruction decoder circuit configured to:
detect a sequence of macro-ops stored in the instruction decode buffer, the sequence of macro-ops including a control-flow macro-op followed by one or more additional macro-ops;
determine a micro-op that is equivalent to the detected sequence of macro-ops; and
forward the micro-op to at least one of the one or more execution resource circuits for execution.
2. The integrated circuit of claim 1 , in which the control-flow macro-op is a branch instruction and the micro-op is not a branch instruction.
3. The integrated circuit of claim 1 , in which the sequence of macro-ops includes an unconditional jump and one or more macro-ops that will be skipped, and the micro-op is a NOP that advances a program counter to a target of the unconditional jump.
4. The integrated circuit of claim 1 , in which the sequence of macro-ops includes an unconditional jump, one or more macro-ops that will be skipped, and a macro-op at a target of the unconditional jump; and the micro-op performs a function of the macro-op at the target of the unconditional jump and advances a program counter to point to a next macro-op after the target of the unconditional jump.
5. The integrated circuit of claim 1 , in which the sequence of macro-ops includes a conditional branch and one or more macro-ops after the conditional branch and before a target of the conditional branch, and the micro-op advances a program counter to the target of the conditional branch.
6. The integrated circuit of claim 1 , in which the sequence of macro-ops includes a conditional branch and one or more macro-ops after the conditional branch and before a target of the conditional branch, and a macro-op at the target of the conditional branch; and the micro-op advances a program counter to point to a next macro-op after the target of the conditional branch.
7. The integrated circuit of claim 1 , in which the sequence of macro-ops includes a conditional branch followed by an unconditional jump.
8. The integrated circuit of claim 1 , in which the sequence of macro-ops includes a conditional branch followed by a jump and link.
9. The integrated circuit of claim 1 , in which the sequence of macro-ops includes a conditional branch followed by a pair of macro-ops implementing a long jump and link.
10. The integrated circuit of claim 1 , in which the sequence of macro-ops includes a conditional branch followed by a pair of macro-ops implementing a long unconditional jump.
11. A method comprising:
fetching macro-ops from memory and storing the macro-ops in an instruction decode buffer;
detecting a sequence of macro-ops stored in the instruction decode buffer, the sequence of macro-ops including a control-flow macro-op followed by one or more additional macro-ops;
determining a micro-op that is equivalent to the detected sequence of macro-ops; and
forwarding the micro-op to at least one execution resource circuit for execution.
12. The method of claim 11 , in which the control-flow macro-op is branch instruction and the micro-op is not a branch instruction.
13. The method of claim 11 , in which the sequence of macro-ops includes an unconditional jump and one or more macro-ops that will be skipped, and the micro-op is a NOP that advances a program counter to a target of the unconditional jump.
14. The method of claim 11 , in which the sequence of macro-ops includes an unconditional jump, one or more macro-ops that will be skipped, and a macro-op at a target of the unconditional jump; and the micro-op performs a function of the macro-op at the target of the unconditional jump and advances a program counter to point to a next macro-op after the target of the unconditional jump.
15. The method of claim 11 , in which the sequence of macro-ops includes a conditional branch and one or more macro-ops after the conditional branch and before a target of the conditional branch, and the micro-op advances a program counter to the target of the conditional branch.
16. The method of claim 11 , in which the sequence of macro-ops includes a conditional branch and one or more macro-ops after the conditional branch and before a target of the conditional branch, and a macro-op at the target of the conditional branch; and the micro-op advances a program counter to point to a next macro-op after the target of the conditional branch.
17. The method of claim 11 , in which the sequence of macro-ops includes a conditional branch followed by an unconditional jump.
18. The method of claim 11 , in which the sequence of macro-ops includes a conditional branch followed by a jump and link.
19. The method of claim 11 , in which the sequence of macro-ops includes a conditional branch followed by a pair of macro-ops implementing a long jump and link.
20. The method of claim 11 , in which the sequence of macro-ops includes a conditional branch followed by a pair of macro-ops implementing a long unconditional jump.