Fusion with destructive instructions

1. An integrated circuit comprising:

a memory system;

a processor core including a one or more execution resource circuitries configured to execute micro-ops to support an instruction set architecture including macro-ops, wherein the processor core is configured to fetch macro-ops from the memory system in a program order; and

a fusion circuitry that is configured to:

detect a sequence of macro-ops stored in a processor pipeline of the processor core, the sequence of macro-ops including a first macro-op identifying a first register as a destination register followed by a second macro-op identifying the first register as both a source register and as a destination register, wherein one or more intervening macro-ops occur between the first macro-op and the second macro-op in the program order;

determine a micro-op that is equivalent to the first macro-op followed by the second macro-op; and

forward the micro-op to at least one of the one or more execution resource circuitries for execution.

2. The integrated circuit of claim 1 , in which the first macro-op is a vector instruction, the second macro-op is a vector instruction, and the first register is a vector register of the instruction set architecture.

3. The integrated circuit of claim 2 , in which the one or more intervening macro-ops are one or more scalar instructions of the instruction set architecture.

4. The integrated circuit of claim 1 , in which the fusion circuitry is configured to detect the sequence of macro-ops when the first macro-op and the second macro-op are stored in an instruction queue in a vector dispatch stage of the processor pipeline, and the one or more intervening macro-ops are sent to a scalar dispatch stage of the processor pipeline that operates in parallel with the vector dispatch stage.

5. The integrated circuit of claim 1 , in which the first macro-op is a stand-alone instruction that can be executed independently of the second macro-op.

6. The integrated circuit of claim 1 , in which vector length is a dynamically configurable parameter of the processor core and the fusion circuitry is configured to:

check that the first macro-op and second macro-op have a same vector length as a condition for determining the micro-op.

7. The integrated circuit of claim 1 , in which the fusion circuitry is configured to:

check that the first macro-op and second macro-op have a same mask argument as a condition for determining the micro-op.

8. The integrated circuit of claim 1 , in which the first macro-op is a vector move instruction and the second macro-op is a destructive vector multiply accumulate instruction.

9. The integrated circuit of claim 1 , in which the first macro-op is a masked vector merge instruction and the second macro-op is a destructive vector multiply accumulate instruction.

10. The integrated circuit of claim 1 , in which the first macro-op is a scalar-to-vector move instruction and the second macro-op is a destructive vector multiply accumulate instruction.

11. The integrated circuit of claim 1 , in which the processor core is an in-order machine.

12. The integrated circuit of claim 1 , in which the processor core is an out-of-order machine that includes an internal in-order decoupled vector queue, and the fusion circuitry is configured to detect the sequence of macro-ops when dispatching vector instructions to reservation stations.

13. A method comprising:

detecting a sequence of macro-ops stored in a processor pipeline of a processor core, the sequence of macro-ops including a first macro-op identifying a first register as a destination register followed by a second macro-op identifying the first register as both a source register and as a destination register, wherein one or more intervening macro-ops occur between the first macro-op and the second macro-op in a program order used to fetch macro-ops from memory;

determining a micro-op that is equivalent to the first macro-op followed by the second macro-op; and

forwarding the micro-op to at least one of one or more execution resource circuitries of the processor core for execution.

14. The method of claim 13 , in which the first macro-op is a vector instruction, the second macro-op is a vector instruction, and the first register is a vector register.

15. The method of claim 14 , in which the one or more intervening macro-ops are one or more scalar instructions.

16. A method comprising:

detecting a sequence of macro-ops stored in a processor pipeline of a processor core, the sequence of macro-ops including a first macro-op identifying a first register as a destination register followed by a second macro-op identifying the first register as both a source register and as a destination register, when the first macro-op and the second macro-op are stored in an instruction queue in a vector dispatch stage of the processor pipeline that operates in parallel with a scalar dispatch stage of the processor pipeline;

determining a micro-op that is equivalent to the first macro-op followed by the second macro-op; and

forwarding the micro-op to at least one of one or more execution resource circuitries of the processor core for execution.

17. The method of claim 16 , in which the first macro-op is a vector instruction, the second macro-op is a vector instruction, and the first register is a vector register.

18. The method of claim 16 , in which the first macro-op is a stand-alone instruction that can be executed independently of the second macro-op.

19. The method of claim 16 , in which vector length is a dynamically configurable parameter of the processor core, comprising:

checking that the first macro-op and second macro-op have a same vector length as a condition for determining the micro-op.

20. The method of claim 16 , comprising:

checking that the first macro-op and second macro-op have a same mask argument as a condition for determining the micro-op.