Display device
The present embodiments disclose a display device. A display device according to an embodiment of the present disclosure comprises a pixel unit including a plurality of pixels, each including a luminous element and a pixel circuit connected to the luminous element, a clock generator configured to generate a plurality of clock signals each corresponding to each of a plurality of subframes constituting a frame, and a parallel to serial converter configured to convert the plurality of clock signals to a serial clock signal and transfer the serial clock signal to the pixel unit, and wherein the pixel circuit of each pixel includes a first pixel circuit configured to control light-emission and non-emission of the luminous element in response to a control signal applied to each of the plurality of subframes and a second pixel circuit configured to store bit values of image data in the frame and generate the control signal based on the stored bit values and the serial clock signal such that each subframe included in the frame is controlled according to each bit value.
1. A display device comprising:
a pixel unit including a plurality of pixels, each including a luminous element and a pixel circuit connected to the luminous element;
a clock generator configured to generate a plurality of clock signals each corresponding to each of a plurality of subframes constituting a frame; and
a parallel to serial converter configured to convert the plurality of clock signals to a serial clock signal and transfer the serial clock signal to the pixel unit; and
wherein the pixel circuit of each pixel includes:
a first pixel circuit configured to control light-emission and non-emission of the luminous element in response to a control signal applied to each of the plurality of subframes; and
a second pixel circuit configured to store bit values of image data in the frame and generate the control signal based on the stored bit values and the serial clock signal such that each subframe included in the frame is controlled according to each bit value.
2. The display device of claim 1 ,
wherein each of the plurality clock signals is generated to include an edge at which level is switched when corresponding subframe starts; and
wherein the serial clock signal includes the edges included in the clock signals.
3. The display device of claim 2 , wherein the second pixel circuit, in response to an edge of the edges included in the serial clock signal being input, is configured to generate the control signal by reading a bit value of a bit corresponding to the input edge.
4. The display device of claim 3 ,
wherein the edges included in the serial clock signal include rising edges and falling edges; and
wherein the second pixel circuit is configured to read a bit value of an odd-numbered bit, in response to a rising edge of the edges included in the serial clock signal being input, and to read a bit value of even-numbered bit, in response to a falling edge of the edges included in the serial clock signal being input.
5. The display device of claim 2 , each of the plurality of clock signals is generated in the form of an impulse generating only a rising edge.
6. The display device of claim 1 , wherein the second pixel circuit includes:
a memory configured to store the bit values of the image data; and
a pulse width modulation (PWM) controller configured to read the bit values from the memory and determine a pulse width of the control signal for the subframe based on a length of the subframe and the bit value corresponding to the subframe.