Always-on audio control for mobile device
In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.
1. A system comprising:
a plurality of audio input devices;
an audio coder/decoder (codec) coupled to the plurality of audio input devices and configured to generate audio samples from sound detected by the plurality of audio input devices;
a memory; and
an integrated circuit coupled to the audio codec and the memory, wherein the integrated circuit includes a first circuit, one or more processors, and a memory controller coupled to the memory;
the first circuit is configured to
detect a predetermined pattern in the audio samples from the audio codec during a time that the memory controller and the one or more processors are powered down;
cause the memory controller and the one or more processors to power up responsive to detecting the predetermined pattern; and
buffer the audio samples that match the predetermined pattern and subsequently-received samples until the memory controller is available to write the audio samples to the memory; and
the audio codec is configured to deactivate one or more of the plurality of audio input devices during the time that the memory controller and the one or more processors are powered down, wherein the audio samples during the time are sampled from active ones of the plurality of audio input devices.
2. The system as recited in claim 1 wherein the plurality of audio input devices comprise a plurality of microphones, and wherein one of the plurality of microphones is in the active ones of the plurality of audio input devices.
3. The system as recited in claim 1 further comprising a plurality of audio output devices coupled to the audio codec, wherein the plurality of audio output devices are deactivated during the time that the memory controller and the one or more processors are powered down.
4. The system as recited in claim 3 wherein the plurality of audio output devices comprise a plurality of speakers.
5. The system as recited in claim 1 wherein the first circuit is configured to write the audio samples that match the predetermined pattern and the subsequently-received samples to the memory through the memory controller.
6. The system as recited in claim 5 wherein the one or more processors are configured to access the audio samples in the memory to verify the match between the predetermined pattern and the audio samples that match the predetermined pattern subsequent to powering up responsive to the first circuit detecting the predetermined pattern.
7. The system as recited in claim 5 wherein the first circuit is configured to supply a plurality of memory controller parameters to the memory controller to program the memory controller for operation, wherein the first circuit is configured to generate write operations to write the audio samples that match the predetermined pattern and the subsequently-received samples subsequent to programming the memory controller.
8. The system as recited in claim 1 wherein the predetermined pattern represents sound comprising a verbal utterance of one or more words.
9. The system as recited in claim 8 wherein the predetermined pattern is captured from a voice of a user.
10. A method comprising:
during a time that a memory controller and one or more processors in an integrated circuit are powered down, receiving a plurality of audio samples in a first circuit within the integrated circuit, wherein the plurality of audio samples are generated by an audio coder/decoder (codec) coupled to a plurality of audio input devices and coupled to the integrated circuit;
detecting, by the first circuit, a predetermined pattern in the audio samples from the audio codec;
causing the memory controller and the one or more processors to power up responsive to detecting the predetermined pattern;
buffering the audio samples that match the predetermined pattern and subsequently-received samples until the memory controller is available to write audio samples to a memory; and
deactivating one or more of the plurality of audio input devices during the time that the memory controller and the one or more processors are powered down, wherein the audio samples during the time are sampled from active ones of the plurality of audio input devices.
11. The method as recited in claim 10 wherein the plurality of audio input devices comprise a plurality of microphones, and wherein one of the plurality of microphones is in the active ones of the plurality of audio input devices.
12. The method as recited in claim 10 further comprising deactivating a plurality of audio output devices coupled to the audio codec during the time that the memory controller and the one or more processors are powered down.
13. The method as recited in claim 12 wherein the plurality of audio output devices comprise a plurality of speakers.
14. The method as recited in claim 10 further comprising, by the first circuit
writing the audio samples that match the predetermined pattern and the subsequently-received samples to memory through the memory controller.
15. The method as recited in claim 14 further comprising accessing, by the one or more processors, the audio samples in the memory to verify the match between the predetermined pattern and the audio samples that match the predetermined pattern subsequent to powering up responsive to the first circuit detecting the predetermined pattern.
16. The method as recited in, claim 14 further comprising:
supplying, by the first circuit, a plurality of memory controller parameters to the memory controller to program the memory controller for operation; and
generating, by the first circuit, write operations to write the audio samples that match the predetermined pattern and the subsequently-received samples subsequent to programming the memory controller.
17. The method as recited in claim 10 wherein the predetermined pattern represents sound comprising a verbal utterance of one or more words.
18. The method as recited in claim 17 further comprising capturing the predetermined pattern from a voice of a user.
19. A system comprising:
a plurality of microphones;
an audio coder/decoder (codec) coupled to the plurality of microphones and configured to generate audio samples from sound detected by the plurality of microphones;
a memory; and
an integrated circuit coupled to the audio codec and the memory, wherein the integrated circuit includes a first circuit, one or more processors, and a memory controller coupled to the memory;
the first circuit is configured to:
detect a predetermined pattern in the audio samples from the audio codec during a time that the memory controller and the one or more processors are powered down;
cause the memory controller and the one or more processors to power up responsive to detecting the predetermined pattern; and
buffer the audio samples that match the predetermined pattern and subsequently received samples until the memory controller is available to write the audio samples to the memory; and
the audio codec is configured to deactivate one or more of the plurality of microphones during the time that the memory controller and the one or more processors are powered down, wherein the audio samples during the time are sampled from active ones of the plurality of microphones.
20. The system as recited in claim 19 further comprising a plurality of speakers coupled to the audio codec, wherein the plurality of speakers are deactivated during the time that the memory controller and the one or more processors are powered down.