IP Library › Granted Patent US 11,862,440
Granted Patent B2
US 11,862,440 · App. 17/373,214 · Granted Jan 2, 2024

Semiconductor processing equipment including electrostatic chuck for plasma processing

Inventors: Jeongil Mun (Hwaseong-si, KR); Jinyoung Park (Anyang-si, KR); Jongwoo Sun (Hwaseong-si, KR); Hyungjoo Lee (Hwaseong-si, KR)
H01J37/32715H01J37/32541H01J37/32568H01L21/6833H01J37/32697
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,862,440
App. No.
17/373,214
Granted
Jan 2, 2024
Kind
B2
Abstract

Semiconductor processing equipment and an electrostatic chuck include a semiconductor having: an upper electrode; a gas supplier connected to the upper electrode; and a substrate supporting structure spaced apart from the upper electrode to define a processing volume. The substrate supporting structure supports a substrate and includes: a lower electrode having a side area disposed outside a step formed at an outer perimeter portion of the lower electrode and a processing area disposed inside the step; a first plate disposed on the lower electrode; an attraction electrode disposed on the first plate; and a second plate disposed on the attraction plate. The second plate supports the substrate in a state in which the substrate is laid on an upper surface of the second plate. Each of the first plate and the second plate includes ceramic. The lower electrode has a maximum height at a central portion of the processing area.

Claims (52)

1. Semiconductor processing equipment comprising:

an upper electrode;

a gas supplier connected to the upper electrode; and

a substrate supporting structure spaced apart from the upper electrode, to define a processing volume, the substrate supporting structure supporting a substrate, wherein:

the substrate supporting structure includes:

a lower electrode comprising a side area disposed outside a step formed at an outer perimeter portion of the lower electrode and a processing area disposed inside the step;

a first plate disposed on the lower electrode;

an attraction electrode disposed on the first plate; and

a second plate disposed on the attraction electrode, the second plate supporting the substrate in a state in which the substrate is laid on an upper surface of the second plate,

each of the first plate and the second plate comprises ceramic,

an upper surface of the lower electrode is non-planar and has a maximum height aligned with a central portion of the processing area, and

the upper surface of the lower electrode comprises a first peak disposed at the central portion of the processing area, a second peak disposed outside the first peak, and a valley disposed between the first peak and the second peak, when viewed in cross-section.

2. The semiconductor processing equipment according to claim 1 , wherein a height difference between the first peak and the valley is 0.2 mm or less.

3. The semiconductor processing equipment according to claim 1 , wherein the lower electrode further comprises a first inflection point disposed between the first peak and the valley in the processing area, and a second inflection point disposed between the second peak and the valley in the processing area, when viewed in cross-section.

4. The semiconductor processing equipment according to claim 1 , wherein the upper surface of the lower electrode is curved in an area overlapping with the processing area.

5. The semiconductor processing equipment according to claim 4 , wherein a lower surface of the first plate is curved in the area overlapping with the processing area.

6. The semiconductor processing equipment according to claim 5 , wherein the first plate has a minimum thickness at a central portion thereof.

7. The semiconductor processing equipment according to claim 1 , wherein an upper surface of the lower electrode has a tilt of 0.01 or less in all portions of the processing area, wherein the tilt is a ratio between a change in height relative to a change in width of along the upper surface of the lower electrode.

8. The semiconductor processing equipment according to claim 1 , wherein the substrate supporting structure comprises a plurality of channels configured to allow a refrigerant to flow therethrough.

9. The semiconductor processing equipment according to claim 8 , wherein the plurality of channels has different vertical widths.

10. The semiconductor processing equipment according to claim 1 , wherein a direction of an incidence vector of an ion incident upon the substrate after being injected from the upper electrode is a vertical direction.

11. The semiconductor processing equipment according to claim 1 , wherein a shape of the upper surface of the lower electrode overlapping the processing area is identical to a shape of a plasma sheath generated in a semiconductor process.

12. The semiconductor processing equipment according to claim 1 , wherein the substrate supporting structure supports the substrate at a position overlapping with the processing area.

13. An electrostatic chuck comprising:

a side area disposed outside a step formed at an outer perimeter portion; and

a processing area disposed inside the step while having a greater height than the side area, wherein:

an upper surface of the processing area has a tilt of 0.01 or less, wherein the tilt is a ratio between a change in height relative to a change in width of along the upper surface of the processing and

electric field vectors in different directions are generated in the processing area,

wherein the upper surface of the processing area comprises a first peak disposed at a central portion of the upper surface, a second peak disposed outside the first peak, and a valley disposed between the first peak and the second peak.

14. The electrostatic chuck according to claim 13 , wherein the first peak has a greater height than the second peak.

15. The electrostatic chuck according to claim 14 , wherein the upper surface of the processing area further comprises a first inflection point disposed between the first peak and the valley and a second inflection point disposed between the second peak and the valley.

16. The electrostatic chuck according to claim 14 , wherein a height difference between the first peak and the valley is 0.2 mm or less.

17. The electrostatic chuck according to claim 13 , wherein the processing area has a maximum height at a central portion thereof.

18. Semiconductor processing equipment comprising:

a chamber;

an upper electrode disposed at a top portion of the chamber;

a gas supplier connected to the upper electrode at an outside of the chamber;

a substrate supporting structure spaced apart from the upper electrode in the chamber to define a processing volume, the substrate supporting structure supporting a substrate;

a vertical rod disposed at a lower side of the substrate supporting structure, the vertical rod extending through a bottom portion of the chamber;

a focus ring disposed at an edge of the substrate supporting structure;

an upper edge ring disposed at an outer edge of the focus ring;

an isolator providing an electrical signal to the substrate supporting structure;

a lower edge ring disposed at a side of the isolator and a lower side of the upper edge ring; and

a ground plate connected to the isolator, wherein:

the substrate supporting structure includes:

a lower electrode comprising a side area disposed outside a step formed at an outer perimeter portion of the lower electrode, and a processing area disposed inside the step;

a first plate disposed on the lower electrode;

an attraction electrode disposed on the first plate; and

a second plate disposed on the attraction electrode, the second plate supporting the substrate in a state in which the substrate is laid on an upper surface of the second plate,

each of the first plate and the second plate comprises ceramic, and

an upper surface of the lower electrode is non-planar and has a maximum height aligned with a central portion of the processing area, and

the upper surface of the lower electrode comprises a first peak disposed at the central portion of the processing area, a second peak disposed outside the first peak, and a valley disposed between the first peak and the second peak, when viewed in cross-section.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2021
From: MUN, JEONGIL; PARK, JINYOUNG; SUN, JONGWOO; LEE, HYUNGJOO
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 056848/0386 →
Priority Claims (1)
KR 10-2020-0176089 · Dec 16, 2020 · national
Continuity (1)
Related Publication 20220189746A1 · Jun 16, 2022