IP Library › Granted Patent US 11,862,528
Granted Patent B2
US 11,862,528 · App. 17/320,981 · Granted Jan 2, 2024

Method for forming semiconductor package

Inventors: Chin-Hua Wang (New Taipei, TW); Po-Yao Lin (Zhudong Township, Hsinchu County, TW); Feng-Cheng Hsu (New Taipei, TW); Shin-Puu Jeng (Hsinchu, TW); Wen-Yi Lin (New Taipei, TW); Shu-Shen Yeh (Taoyuan, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H01L23/367H01L21/4882H01L21/563H01L23/3128H01L23/3736H01L23/433H01L25/0655H01L25/105
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Quick Facts
Patent No.
US 11,862,528
App. No.
17/320,981
Granted
Jan 2, 2024
Kind
B2
Abstract

A method of forming a semiconductor package is provided. The method includes mounting a chip on a package substrate. The method further includes placing a heat spreader over the chip and applying a thermal interface material to a first surface of the heat spreader facing the chip. The heat spreader is flexible. In addition, the method includes attaching the heat spreader to the chip through the thermal interface material by rolling a rod over a second surface of the heat spreader, and the second surface is opposite to the first surface.

Claims (51)

1. A method of forming a semiconductor package, comprising:

mounting a chip on a package substrate;

placing a heat spreader over the chip and applying a thermal interface material to a first surface of the heat spreader facing the chip, wherein the heat spreader is flexible;

attaching the heat spreader to the chip through the thermal interface material by rolling a rod over a second surface of the heat spreader, the second surface being opposite to the first surface;

mounting a second chip on the package substrate; and

dispensing a underfill material between the package substrate and the chip, and between the package substrate and the second chip, wherein the underfill material continuously extends under the chip and the second chip.

2. The method as claimed in claim 1 , further comprising performing a compression and curing process to cure the thermal interface material.

3. The method as claimed in claim 1 , further comprising:

dispensing a underfill material into a space between the chip and the package substrate; and

forming a molding compound over the package substrate so that the molding compound encapsulates a side periphery of the chip and exposes a top surface of the chip; wherein

the attachment process further comprises attaching the heat spreader to the top surface of the chip and a top surface of the molding compound through the thermal interface material.

4. The method as claimed in claim 3 , further comprising:

forming a metal feature in the molding compound before the attachment process; and

performing a drilling process to form an opening in the heat spreader and the thermal interface material to expose the metal feature.

5. The method as claimed in claim 1 , wherein the chip and the second chip have different heights.

6. The method as claimed in claim 1 , further comprising providing a metal heat sink over a top surface of the chip and a top surface of the second chip, wherein a distance between the metal heat sink and the chip is different from a distance between the metal heat sink and the second chip.

7. The method as claimed in claim 1 , wherein the first chip and the second chip have different heights.

8. A method of forming a semiconductor package, comprising:

providing a package substrate on a first carrier;

bonding a first chip on the package substrate;

forming a molding compound surrounding the first chip;

forming a heat spreader and a thermal interface material over the first chip and the molding compound by rolling a rod over the heat spreader, wherein the heat spreader is flexible;

bonding the heat spreader on a second carrier; and

forming an electrical connector on the package substrate, wherein the electrical connector and the first chip are disposed on opposite sides of the package substrate.

9. The method as claimed in claim 8 , further comprising:

affixing the electrical connector on a dicing tape;

removing the first carrier;

dicing the package substrate; and

removing the dicing tape.

10. The method as claimed in claim 8 , further comprising bonding a second chip on the package substrate, wherein the heat spreader and the thermal interface material continuously extend above the first chip and the second chip.

11. The method as claimed in claim 10 , wherein the first chip and the second chip have different heights, and the method further comprises providing a heat sink over the heat spreader, wherein the heat sink has a bottom surface that conforms a profile of a top surface of the first chip and a top surface of the second chip.

12. The method as claimed in claim 11 , wherein the heat spreader and the heat sink have different heat conductivities.

13. The method as claimed in claim 10 , further comprising forming a underfill layer extending under the first chip and the second chip, wherein a portion of the molding compound is between the first chip and the second chip and in contact with the underfill layer.

14. The method as claimed in claim 8 , further comprising forming an opening on the heat spreader.

15. A method of forming a semiconductor package, comprising:

forming a conductive structure over a first package substrate;

bonding a first chip on the first package substrate;

forming a molding compound surrounding the conductive structure and the first chip;

forming a first heat spreader and a first thermal interface material over the conductive structure, the first chip, and the molding compound by rolling a rod over the first heat spreader, wherein the first heat spreader is flexible; and

forming an opening on the first heat spreader and the first thermal interface material to expose the conductive structure.

16. The method as claimed in claim 15 , further comprising:

bonding a second chip on a first side of a second package substrate;

forming a second heat spreader and a second thermal interface material over the second chip;

bonding an electrical connector on a second side of the second package substrate, wherein the first side is opposite to the second side; and

connecting the electrical connector to the conductive structure through the opening.

17. The method as claimed in claim 16 , further comprising:

forming a first underfill layer between the first chip and the first package substrate; and

forming a second underfill layer between the second chip and the second package substrate, wherein the first chip is disposed between the first underfill layer and the second underfill layer.

18. The method as claimed in claim 16 , wherein a top surface of the first chip faces the first heat spreader and the second heat spreader.

19. The method as claimed in claim 16 , wherein a gap is formed between the second package substrate and the first heat spreader.

20. The method as claimed in claim 15 , wherein the opening has a tilted side surface.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 14, 2021
From: WANG, CHIN-HUA; LIN, PO-YAO; HSU, FENG-CHENG; JENG, SHIN-PUU; LIN, WEN-YI; YEH, SHU-SHEN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 056249/0185 →
Continuity (3)
Division 16275518 · Feb 14, 2019
Provisional Application 62718545 · Aug 14, 2018
Related Publication 20210272869A1 · Sep 2, 2021