Chip and manufacturing method thereof, and electronic device
Embodiments of this application provide a chip and a manufacturing method thereof, and an electronic device, and belong to the field of chip heat dissipation technologies. The chip includes a die and a thermal conductive sheet. An active surface of the die is connected to the thermal conductive sheet by using a first bonding layer. Heat generated at a part with a relatively high temperature on the active surface of the die can be quickly conducted and dispersed by using the thermal conductive sheet, so that temperatures on the active surface are evenly distributed to avoid an excessively high local temperature of the chip, thereby preventing running of the chip from being affected.
1. A chip, comprising:
a die; and
a thermal conductive sheet, wherein an active surface of the die is connected to the thermal conductive sheet by using a first bonding layer, wherein thermal resistance of the first bonding layer is less than a threshold, and wherein the thermal conductive sheet comprises one or more of a single crystal diamond film, a polycrystalline diamond film, a boron nitride film, or a boron arsenide film.
2. The chip according to claim 1 , further comprising:
a plurality of conductive pillars run through the thermal conductive sheet,
wherein the first bonding layer comprises an insulated connection layer and a plurality of electrical interconnection structures, wherein the electrical interconnection structures are located in the insulated connection layer; and
a plurality of pads of the active surface connected to the conductive pillars through bonding by using the electrical interconnection structures, wherein a region of the active surface other than the pads is connected to the thermal conductive sheet through bonding by using the insulated connection layer.
3. The chip according to claim 1 , further comprising:
a plurality of conductive pillars run through the thermal conductive sheet; and
wherein the first bonding layer comprises an insulated connection layer, wherein the conductive pillars are deposited on pads of the active surface, and wherein a region of the active surface other than the pads is connected to the thermal conductive sheet through bonding by using the insulated connection layer.
4. The chip according to claim 2 , wherein the electrical interconnection structures are made from one or more of: Cu, Ni, W, CuSn, or AuSn.
5. The chip according to claim 2 , wherein the insulated connection layer is made from one or more of: SiO2, AlN, SiC, benzocyclobutene, polyimide, or near ultraviolet negative photoresist.
6. The chip according to claim 2 , wherein the thermal resistance of the first bonding layer is less than the threshold including 1 Kmm 2 /W.
7. The chip according to claim 1 , further comprising at least two dies and at least one thermal conductive sheet, and wherein the dies and the thermal conductive sheet are stacked alternately.
8. The chip according to claim 7 , wherein the thermal conductive sheet is connected to a passive surface of an adjacent die by using a second bonding layer, and wherein a structure of the second bonding layer is the same as that of the first bonding layer.
9. The chip according to claim 1 , wherein the chip comprises a seed layer located between the conductive pillars and the thermal conductive sheet.
10. The chip according to claim 1 , further comprising:
a circuit board, wherein the die and the thermal conductive sheet are located on the circuit board, and wherein in an arrangement direction of the die and the thermal conductive sheet, the thermal conductive sheet is adjacent to the circuit board.
11. The chip according to claim 1 , further comprising:
a radiating fin connected to a passive surface of an outermost die by using a third bonding layer.
12. The chip according to claim 11 , wherein the third bonding layer is made from a metal material, and the metal material comprises one or more of: Au, AuSn, Cu, CuSn, Ag, or AgSn; or
the third bonding layer is made from a nonmetallic material, and the nonmetallic material comprises one or more of: SiO2, SiC, AlN, or Si.
13. The chip according to claim 1 , wherein a projection of the die on a surface of the connected thermal conductive sheet is located within the surface or overlaps the surface.
14. The chip according to claim 1 , wherein a thickness of the die is 15 μm to 500 μm.
15. The chip according to claim 1 , wherein a thickness of the thermal conductive sheet is 50 μm to 500 μm.
16. An electronic device, comprising:
a chip having a die and a thermal conductive sheet, wherein an active surface of the die is connected to the thermal conductive sheet by using a first bonding layer, wherein thermal resistance of the first bonding layer is less than a threshold, and wherein the thermal conductive sheet comprises one or more of a single crystal diamond film, a polycrystalline diamond film, a boron nitride film, or a boron arsenide film.
17. The electronic device according to claim 16 , wherein the chip further comprises:
a plurality of conductive pillars run through the thermal conductive sheet,
wherein the first bonding layer comprises an insulated connection layer and a plurality of electrical interconnection structures located in the insulated connection layer; and
a plurality of pads of the active surface are connected to the conductive pillars through bonding by using the electrical interconnection structures, wherein a region of the active surface other than the pads is connected to the thermal conductive sheet through bonding by using the insulated connection layer.
18. The electronic device according to claim 16 , wherein the chip further comprises:
a plurality of conductive pillars run through the thermal conductive sheet; and
wherein the first bonding layer comprises an insulated connection layer, wherein the conductive pillars are deposited on pads of the active surface, and wherein a region of the active surface other than the pads is connected to the thermal conductive sheet through bonding by using the insulated connection layer.
19. The electronic device according to claim 17 , wherein the electrical interconnection structures are made from one or more of: Cu, Ni, W, CuSn, or AuSn.