Integrated substrate structure, electronic assembly, and manufacturing method thereof
An integrated substrate, an electronic assembly, and manufacturing methods thereof are provided. The integrated substrate structure includes a coarse redistribution structure, fine redistribution segments, and conductive connectors. The coarse redistribution structure includes a coarse dielectric layer and a coarse circuitry embedded therein. The fine redistribution segments disposed over the coarse redistribution structure and disposed side by side and apart from one another. The respective fine redistribution segment includes a fine dielectric layer thinner than the coarse dielectric layer, and a fine circuitry embedded in the fine dielectric layer. The fine circuitry includes a dimension and a pitch finer than those of the coarse circuitry, and a layout density of the fine circuitry is denser than that of the coarse circuitry. The conductive connectors are interposed between the coarse redistribution structure and the fine redistribution segments, and the coarse circuitry is electrically coupled to the fine circuitry through the conductive connectors.
1. An integrated substrate structure for coupling a fine-pitched chip, comprising:
a coarse redistribution structure comprising a coarse dielectric layer and a coarse circuitry embedded in the coarse dielectric layer;
a plurality of fine redistribution segments disposed over the coarse redistribution structure and coupled to the fine-pitched chip, the plurality of fine redistribution segments being disposed side by side and spatially apart from one another, each of the plurality of fine redistribution segments comprising:
a fine dielectric layer being thinner than the coarse dielectric layer; and
a fine circuitry embedded in the fine dielectric layer, the fine circuitry comprising a dimension and a pitch finer than those of the coarse circuitry of the coarse redistribution structure, and a layout density of the fine circuitry being denser than a layout density of the coarse circuitry;
a plurality of conductive connectors interposed between and in direct contact with the coarse redistribution structure and the plurality of fine redistribution segments, and the coarse circuitry being electrically coupled to the fine circuitry through the plurality of conductive connectors, wherein each of the plurality of conductive connectors comprises a solder joint; and
a plurality of underfill layers interposed between the coarse redistribution structure and the plurality of fine redistribution segments, wherein each of the plurality of underfill layers surrounds and directly contacts the corresponding plurality of conductive connectors located between the coarse redistribution structure and the corresponding plurality of fine redistribution segments, wherein the plurality of underfill layers spatially apart from one another.
2. The integrated substrate structure of claim 1 , further comprising:
an embedded chip interposed between the coarse redistribution structure and the one of the plurality of fine redistribution segments, and the embedded chip being physically and electrically connected to the fine circuitry of the one of the plurality of fine redistribution segments,
wherein the embedded chip and the conductive connectors surrounding the embedded chip being embedded in one of the plurality of underfill layers.
3. The integrated substrate structure of claim 2 , wherein each of the plurality of conductive connectors which surrounds the embedded chip further comprises:
a conductive pillar physically and electrically connected to the fine circuitry of the one of the plurality of fine redistribution segments,
wherein the solder joint is underlying the conductive pillar and physically and electrically connected to the coarse circuitry of the coarse redistribution structure.
4. The integrated substrate structure of claim 1 , further comprising:
a plurality of insulating segments spatially apart from one another, each of the plurality of fine redistribution segments being encapsulated by one of the plurality of insulating segments, and the plurality of insulating segments being spatially apart from the coarse redistribution structure.
5. The integrated substrate structure of claim 4 , wherein:
the one of the plurality of fine redistribution segments comprises a top surface, a bottom surface opposite to the top surface, and a sidewall connected to the top surface and the bottom surface, and
a corresponding one of the plurality of insulating segments covers the sidewall and the bottom surface of the one of the plurality of fine redistribution segments, and the plurality of conductive connectors which are connected to the bottom surface of the one of the plurality of fine redistribution segments are embedded in the corresponding one of the plurality of insulating segments.
6. The integrated substrate structure of claim 5 , wherein the top surface of the one of the plurality of fine redistribution segments is substantially coplanar with a top surface of the corresponding one of the plurality of insulating segments.
7. The integrated substrate structure of claim 4 , further comprising:
an embedded chip interposed between the coarse redistribution structure and the one of the plurality of fine redistribution segments and embedded inside one of the plurality of insulating segments, and the embedded chip being physically and electrically connected to the fine circuitry of the one of the plurality of fine redistribution segments,
wherein one of the plurality of underfill layers interposed between the coarse redistribution structure and the one of the plurality of insulating segments.
8. The integrated substrate structure of claim 1 , further comprising:
a heat-dissipating feature embedded inside the coarse redistribution structure, wherein the coarse circuitry comprises coarse conductive patterns stacked upon one another and a conductive through via vertically connected the coarse conductive patterns, and the conductive through via penetrates through the heat-dissipating feature which is laterally covered by the coarse dielectric layer.
9. The integrated substrate structure of claim 1 , wherein the coarse redistribution structure comprises a top side and a bottom side, a portion of the plurality of fine redistribution segments is disposed at the top side of the coarse redistribution structure, and another portion of the plurality of fine redistribution segments is disposed at the bottom side of the coarse redistribution structure.
10. The integrated substrate structure of claim 9 , further comprising:
an embedded chip interposed between the coarse redistribution structure and the one of the plurality of fine redistribution segments disposed at the top side, and the embedded chip being physically and electrically connected to the fine circuitry of the one of the plurality of fine redistribution segments,
wherein the embedded chip and the conductive connectors surrounding the embedded chip being embedded in one of the plurality of underfill layers.
11. An electronic assembly, comprising:
an integrated substrate structure according to claim 1 ; and
a chip structure disposed on and electrically connected to one of the plurality of fine redistribution segments of the integrated substrate structure; and
a power supply module disposed below and electrically coupled to the coarse redistribution structure.
12. The integrated substrate structure of claim 3 , wherein the one of the plurality of underfill layers encloses a side surface of the conductive pillar and the solder joint is physically and electrically connected to the conductive pillar.
13. An integrated substrate structure for coupling a fine-pitched chip, comprising:
a coarse redistribution structure comprising a coarse dielectric layer and a coarse circuitry embedded in the coarse dielectric layer;
a plurality of fine redistribution segments disposed over the coarse redistribution structure and coupled to the fine-pitched chip, the plurality of fine redistribution segments being disposed side by side and spatially apart from one another, each of the plurality of fine redistribution segments comprising:
a fine dielectric layer being thinner than the coarse dielectric layer; and
a fine circuitry embedded in the fine dielectric layer, the fine circuitry comprising a dimension and a pitch finer than those of the coarse circuitry of the coarse redistribution structure, and a layout density of the fine circuitry being denser than a layout density of the coarse circuitry;
a plurality of conductive connectors interposed between the coarse redistribution structure and the plurality of fine redistribution segments, and the coarse circuitry being electrically coupled to the fine circuitry through the plurality of conductive connectors, wherein each of the plurality of conductive connectors comprises a solder joint;
an underfill layer interposed between the coarse redistribution structure and one of the plurality of fine redistribution segments, wherein the underfill layer surrounds and directly contacts the corresponding plurality of conductive connectors located between the coarse redistribution structure and the one of the plurality of fine redistribution segments; and
a plurality of insulating segments spatially apart from one another, each of the plurality of fine redistribution segments being encapsulated by one of the plurality of insulating segments, and the plurality of insulating segments being spatially apart from the coarse redistribution structure,
wherein the plurality of conductive connectors which are connected to the one of the plurality of fine redistribution segments are embedded in the corresponding one of the plurality of insulating segments.
14. The integrated substrate structure of claim 13 , wherein each of the plurality of conductive connectors further comprises:
a conductive pillar physically and electrically connected to the fine circuitry of the one of the plurality of fine redistribution segments,
wherein the one of the plurality of insulating segments encloses a side surface of the conductive pillar, and
the solder joint is underlying the conductive pillar and physically and electrically connected to the coarse circuitry of the coarse redistribution structure and the conductive pillar.
15. An integrated substrate structure for coupling a fine-pitched chip, comprising:
a coarse redistribution structure comprising a coarse dielectric layer and a coarse circuitry embedded in the coarse dielectric layer;
a plurality of fine redistribution segments disposed over the coarse redistribution structure and coupled to the fine-pitched chip, the plurality of fine redistribution segments being disposed side by side and spatially apart from one another, each of the plurality of fine redistribution segments comprising:
a fine dielectric layer being thinner than the coarse dielectric layer; and
a fine circuitry embedded in the fine dielectric layer, the fine circuitry comprising a dimension and a pitch finer than those of the coarse circuitry of the coarse redistribution structure, and a layout density of the fine circuitry being denser than a layout density of the coarse circuitry;
a plurality of conductive connectors interposed between the coarse redistribution structure and the plurality of fine redistribution segments, and the coarse circuitry being electrically coupled to the fine circuitry through the plurality of conductive connectors, wherein each of the plurality of conductive connectors comprises a solder joint;
an underfill layer interposed between the coarse redistribution structure and one of the plurality of fine redistribution segments, wherein the underfill layer surrounds and directly contacts the corresponding plurality of conductive connectors located between the coarse redistribution structure and the one of the plurality of fine redistribution segments; and
an embedded chip interposed between the coarse redistribution structure and the one of the plurality of fine redistribution segments, and the embedded chip being physically and electrically connected to the fine circuitry of the one of the plurality of fine redistribution segments,
wherein the embedded chip and the conductive connectors surrounding the embedded chip being embedded in the underfill layer and the underfill layer encloses side surfaces and a bottom surface of the embedded chip.
16. The integrated substrate structure of claim 15 , wherein each of the plurality of conductive connectors which surrounds the embedded chip further comprises:
a conductive pillar physically and electrically connected to the fine circuitry of the one of the plurality of fine redistribution segments,
wherein the underfill layer encloses a side surface of the conductive pillar, and
the solder joint is underlying the conductive pillar and physically and electrically connected to the coarse circuitry of the coarse redistribution structure and the conductive pillar.