Selectable monolithic or external scalable die-to-die interconnection system methodology
Multi-die structures and methods of fabrication are described. In an embodiment, a multi-die structure includes a first die, a second die, and die-to-die routing connecting the first die to the second die. The die-to-die interconnection may be monolithically integrated as a chip-level die-to-die routing, or external package-level die-to-die routing.
1. A multi-die structure comprising:
a first front-end-of-the line (FEOL) die area of a first die patterned into a semiconductor substrate and a second FEOL die area of a second die patterned into the semiconductor substrate, the second FEOL die area separate from the first FEOL die area;
a first selection device within the first FEOL die area;
a second selection device within the second FEOL die area; and
a back-end-of-the-line (BEOL) build-up structure spanning over the first FEOL die area and the second FEOL die area, the BEOL build-up structure comprising:
a chip-level die-to-die routing connecting the first selection device with the second selection device;
a first inter-chip routing connected to the first selection device; and
a second inter-chip routing with the second selection device.
2. The multi-die structure of claim 1 , wherein the first inter-chip routing is electrically connected to an electrically open first terminal, and the second inter-chip routing is electrically connected to an electrically open second terminal.
3. The multi-die structure of claim 2 , wherein the first terminal and the second terminal are both buried within the BEOL build-up structure beneath a face side of the BEOL build-up structure.
4. The multi-die structure of claim 1 , wherein the BEOL build-up structure includes additional routing connecting the first FEOL die and the second FEOL die area to a plurality of chip-level landing pads.
5. The multi-die structure of claim 4 , further comprising a corresponding plurality of solder bumps on the plurality of chip-level landing pads.
6. The multi-die structure of claim 1 , wherein the BEOL build-up structure includes a first metallic seal adjacent the first FEOL die area, and a second metallic seal adjacent the second FEOL die area, wherein the chip-level die-to-die routing extends through a first opening in the first metallic seal and a second opening in the second metallic seal.
7. The multi-die structure of claim 1 , wherein the BEOL build-up structure includes a first metallic seal adjacent the first FEOL die area, and a second metallic seal adjacent the second FEOL die area, wherein the chip-level die-to-die routing extends over the first metallic seal and the second metallic seal.
8. The multi-die structure of claim 7 , wherein:
the first FEOL die area includes a third selection device, and the first BEOL build-up structure includes an open chip-level die-to-die routing connected to the third selection device; and
the open chip-level die-to-die routing extends through a second opening in the first metallic seal.
9. The multi-die structure of claim 8 , wherein the open chip-level die-to-die routing terminates at a side edge of the first die.
10. The multi-die structure of claim 1 , wherein the first FEOL die area includes a transceiver connected to an input of the first selection device, and the second FEOL die area includes a receiver connected to an output of the second selection device.
11. The multi-die structure of claim 1 , further comprising a through silicon via connected to the first selection device.