Method for fabricating fin structure for fin field effect transistor
The invention provides a method for fabricating a fin structure for fin field effect transistor, including following steps. Providing a substrate, including a fin structure having a silicon fin and a single mask layer just on a top of the silicon fin, the single mask layer being as a top portion of the fin structure. Forming a stress buffer layer on the substrate and conformally covering over the fin structure. Performing a nitridation treatment on the stress buffer layer to have a nitride portion. Perform a flowable deposition process to form a flowable dielectric layer to cover over the fin structures. Annealing the flowable dielectric layer. Polishing the flowable dielectric layer, wherein the nitride portion of the stress buffer layer is used as a polishing stop.
1. A method for fabricating a fin structure for fin field effect transistor, comprising:
providing a substrate, including a fin structure having a silicon fin and a single mask layer just on a top of the silicon fin, the single mask layer being as a top portion of the fin structure;
forming a stress buffer layer on the substrate and conformally covering over the fin structure;
forming an atomic layer deposition (ALD) layer between the stress buffer layer and each of the silicon fins;
performing a nitridation treatment on the stress buffer layer to have a nitride portion;
perform a flowable deposition process to form a flowable dielectric layer to cover over the fin structures;
annealing the flowable dielectric layer; and
polishing the flowable dielectric layer, wherein the nitride portion of the stress buffer layer is used as a polishing stop.
2. The method for fabricating the fin structure as recited in claim 1 , further comprising performing an etching back process on the flowable dielectric layer, the single mask layer, the stress buffer layer and the atomic layer deposition layer, to expose an upper part of the silicon fin.
3. The method for fabricating the fin structure as recited in claim 1 , wherein the flowable deposition process is a flowable chemical vapor deposition (FCVD) process for flowable oxide material.
4. The method for fabricating the fin structure as recited in claim 1 , wherein the substrate includes a silicon wafer or a silicon on insulator (SOI) substrate.
5. The method for fabricating the fin structure as recited in claim 1 , wherein the single mask layer includes an oxide mask layer.
6. The method for fabricating the fin structure as recited in claim 1 , wherein the nitride portion in the stress buffer layer is a nitriding part of the stress buffer layer due to a partial nitridation on the stress buffer layer.
7. The method for fabricating the fin structure as recited in claim 1 , wherein the nitride portion is a silicon nitride portion and the stress buffer layer is an amorphous silicon layer.
8. The method for fabricating the fin structure as recited in claim 1 , further comprising:
performing a dielectric etching process to expose an upper portion of the silicon fins,
wherein a top of each of the silicon fins is a round-like shape in a cross-section view due to the dielectric etching process.