Integrated circuit device
An integrated circuit device includes a fin-type active region disposed on a substrate and extending in a first horizontal direction, a gate line disposed on the fin-type active region and extending in a second horizontal direction intersecting the first horizontal direction, the gate line including, a connection protrusion portion including a protrusion top surface at a first vertical level from the substrate, and a main gate portion including a recess top surface extending in the second horizontal direction from the connection protrusion portion, the recess top surface being at a second vertical level lower than the first vertical level, a gate contact disposed on the gate line and connected to the connection protrusion portion, a source/drain region disposed on the fin-type active region and disposed adjacent to the gate line, and a source/drain contact disposed on the source/drain region.
1. An integrated circuit device comprising:
a fin-type active region disposed on a substrate and extending in a first horizontal direction;
a gate line disposed on the fin-type active region and extending in a second horizontal direction intersecting the first horizontal direction, the gate line comprising:
a connection protrusion portion comprising a protrusion top surface at a first vertical level from the substrate, and
a main gate portion comprising a recess top surface extending in the second horizontal direction from the connection protrusion portion, the recess top surface being at a second vertical level lower than the first vertical level;
a gate contact disposed on the gate line and connected to the connection protrusion portion;
a source/drain region disposed on the fin-type active region and disposed adjacent to the gate line; and
a source/drain contact disposed on the source/drain region, the source/drain contact comprising an uppermost surface at a third vertical level higher than the first vertical level.
2. The integrated circuit device of claim 1 , wherein the substrate comprises:
a device region; and
an inter-device isolation region defining the device region,
wherein the main gate portion extends in the second horizontal direction in the device region and the inter-device isolation region, and
wherein the connection protrusion portion and the gate contact are disposed in the device region.
3. The integrated circuit device of claim 1 , wherein the substrate comprises:
a device region; and
an inter-device isolation region defining the device region,
wherein the main gate portion extends in the second horizontal direction in the device region and the inter-device isolation region, and
wherein the connection protrusion portion and the gate contact are disposed in the inter-device isolation region.
4. The integrated circuit device of claim 1 , wherein the substrate comprises:
a first device region; and
a second device region disposed apart from the first device region,
wherein the connection protrusion portion is disposed in one among the first device region and the second device region, and
wherein the recess top surface is disposed in another one among the first device region and the second device region.
5. The integrated circuit device of claim 1 , wherein the gate contact and the source/drain contact are staggeredly arranged not to be disposed on a straight line in the first horizontal direction.
6. The integrated circuit device of claim 1 , wherein the gate contact and the source/drain contact are disposed on a straight line in the first horizontal direction.
7. The integrated circuit device of claim 1 , further comprising a capping insulation pattern covering the protrusion top surface of the connection protrusion portion and the recess top surface of the main gate portion,
wherein the gate contact is disposed through the capping insulation pattern and contacts the protrusion top surface.
8. The integrated circuit device of claim 1 , further comprising a nanosheet stack facing a fin top surface of the fin-type active region and disposed apart from the fin top surface in a vertical direction, the nanosheet stack comprising a plurality of nanosheets having different vertical distances from the fin top surface,
wherein the gate line further comprises at least one sub gate portion connected to the main gate portion as one body and interposed between two adjacent nanosheets among the plurality of nanosheets, and
wherein the recess top surface is higher than a top surface of the nanosheet stack in the vertical direction.
9. The integrated circuit device of claim 1 , further comprising a nanosheet stack facing a fin top surface of the fin-type active region and disposed apart from the fin top surface in a vertical direction, the nanosheet stack comprising a plurality of nanosheets having different vertical distances from the fin top surface,
wherein the recess top surface is lower than or equal to a vertical level of a top surface of the nanosheet stack.
10. The integrated circuit device of claim 1 , further comprising:
a nanosheet stack comprising at least one nanosheet facing a fin top surface of the fin-type active region and disposed apart from the fin top surface; and
a gate dielectric layer comprising a first portion covering a surface of the at least one nanosheet,
wherein the recess top surface is lower than or equal to a vertical level of a top surface of the first portion of the gate dielectric layer.
11. The integrated circuit device of claim 1 , wherein the substrate comprises:
a first device region; and
a second device region disposed apart from the first device region,
wherein the fin-type active region comprises:
a first fin-type active region extending in the first horizontal direction in the first device region; and
a second fin-type active region extending in the first horizontal direction in the second device region,
wherein the integrated circuit device further comprises:
a first nanosheet stack comprising at least one first nanosheet facing a first fin top surface of the first fin-type active region and disposed apart from the first fin top surface in a vertical direction, the at least one first nanosheet being surrounded by the gate line;
a second nanosheet stack comprising at least one second nanosheet facing a second fin top surface of the second fin-type active region and disposed apart from the second fin top surface in the vertical direction, the at least one second nanosheet being surrounded by the gate line,
wherein the first fin-type active region overlaps the protrusion top surface in the vertical direction,
wherein the second fin-type active region overlaps the recess top surface in the vertical direction, and
wherein a number of the at least one second nanosheet is less than a number of the at least one first nanosheet.
12. The integrated circuit device of claim 1 , further comprising:
a capping insulation pattern covering the recess top surface of the main gate portion and the protrusion top surface of the connection protrusion portion;
at least one nanosheet facing a fin top surface of the fin-type active region and disposed apart from the fin top surface in a vertical direction; and
a semiconductor oxide piece interposed between the source/drain region and the capping insulation pattern at a position overlapping the at least one nanosheet in the vertical direction.
13. The integrated circuit device of claim 1 , further comprising a nanosheet stack comprising at least one nanosheet facing a fin top surface of the fin-type active region and disposed apart from the fin top surface in a vertical direction,
wherein the connection protrusion portion comprises a protrusion sidewall comprising a lateral recess recessed in the first horizontal direction at a position overlapping the at least one nanosheet in the vertical direction.
14. The integrated circuit device of claim 1 , further comprising:
a nanosheet stack comprising at least one nanosheet facing a fin top surface of the fin-type active region and disposed apart from the fin top surface in a vertical direction,
wherein the connection protrusion portion comprises a protrusion sidewall overlapping the at least one nanosheet in the vertical direction, the protrusion sidewall comprising a lateral recess recessed in the first horizontal direction at a position overlapping the at least one nanosheet in the vertical direction; and
a semiconductor oxide piece buried into the lateral recess and comprising a portion overlapping the at least one nanosheet in the vertical direction.
15. An integrated circuit device comprising:
a substrate comprising:
a first region; and
a second region disposed apart from the first region;
a first fin-type active region extending in a first horizontal direction in the first region;
a first gate line extending in a second horizontal direction intersecting the first horizontal direction, in the first fin-type active region, the first gate line comprising a top surface at a first vertical level from the substrate;
a second fin-type active region extending in the first horizontal direction in the second region; and
a second gate line extending in the second horizontal direction in the second fin-type active region, the second gate line comprising a recess top surface at a second vertical level lower than the first vertical level,
wherein the second gate line further comprises a connection protrusion portion protruding in a vertical direction from the recess top surface, the connection protrusion portion comprising a protrusion top surface at the first vertical level.
16. The integrated circuit device of claim 15 , further comprising:
a first gate contact contacting the top surface of the first gate line in the first region; and
a second gate contact connected to the second gate line in the second region,
wherein the top surface of the first gate line extends over a total length of the first gate line, and
wherein the second gate contact contacts the protrusion top surface.
17. The integrated circuit device of claim 15 , further comprising:
a first gate contact contacting the top surface of the first gate line in the first region, the first gate contact having a first vertical length; and
a second gate contact contacting the recess top surface of the second gate line in the second region, the second gate contact having a second vertical length greater than the first vertical length,
wherein the top surface of the first gate line extends over a total length of the first gate line, and
wherein the recess top surface of the second gate line extends over a total length of the second gate line.
18. The integrated circuit device of claim 15 , further comprising:
a first nanosheet stack comprising at least one first nanosheet facing a first fin top surface of the first fin-type active region and disposed apart from the first fin top surface in a vertical direction in the first region, the at least one first nanosheet being surrounded by the first gate line; and
a second nanosheet stack comprising at least one second nanosheet facing a second fin top surface of the second fin-type active region and disposed apart from the second fin top surface in the vertical direction in the second region, the at least one second nanosheet being surrounded by the second gate line,
wherein a number of the at least one second nanosheet is less than a number of the at least one first nanosheet.
19. An integrated circuit device comprising:
a substrate comprising:
a first device region; and
a second device region disposed apart from the first device region;
a first fin-type active region extending in a first horizontal direction in the first device region;
a second fin-type active region extending in the first horizontal direction in the second device region;
a first nanosheet stack comprising at least one first nanosheet facing a first fin top surface of the first fin-type active region and disposed apart from the first fin top surface in a vertical direction;
a second nanosheet stack comprising at least one second nanosheet facing a second fin top surface of the second fin-type active region and disposed apart from the second fin top surface in the vertical direction;
a gate line comprising:
a connection protrusion portion extending in a second horizontal direction intersecting the first horizontal direction, in the first device region and the second device region, the connection protrusion portion comprising a protrusion top surface at a first vertical level from the substrate;
a main gate portion comprising a recess top surface extending in the second horizontal direction from the connection protrusion portion, the recess top surface being at a second vertical level lower than the first vertical level; and
a plurality of sub gate portions connected to the main gate portion as one body and surrounding the first nanosheet stack and the second nanosheet stack;
a gate contact disposed on the gate line and contacting the connection protrusion portion;
a source/drain region disposed on one among the first fin-type active region and the second fin-type active region and disposed adjacent to the gate line; and
a source/drain contact disposed on the source/drain region, the source/drain contact comprising an uppermost surface at a third vertical level higher than the first vertical level.
20. The integrated circuit device of claim 19 , wherein a number of the at least one first nanosheet differs from a number of the at least one second nanosheet.