Display device and electronic device
View Patent ↗It is an object to provide a display device which can favorably display a image without delayed or distorted signals. The display device includes a first gate driver and a second gate driver. The first gate driver and the second gate driver each include a plurality of flip flop circuits and a plurality of transfer signal generation circuits. Both the flip flop circuit and the transfer signal generation circuit are circuits which output a signal inputted to a first input terminal with a half clock cycle delay. In addition, an output terminal of the transfer signal generation circuit is directly connected to a first input terminal of the flip flop circuit in the next stage. Therefore, delay and distortion of the signal which is inputted from the transfer signal generation circuit to the flip flop circuit can be reduced.
1. A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to a third wiring,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to a fourth wiring,
wherein a gate of the third transistor is electrically connected to the fourth wiring,
wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the first transistor,
wherein a gate of the fourth transistor is electrically connected to a fifth wiring,
wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the second transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the third wiring,
wherein a gate of the fifth transistor is electrically connected to the gate of the first transistor,
wherein one of a source and a drain of the sixth transistor is electrically connected to the fifth wiring,
wherein the other of the source and the drain of the sixth transistor is electrically connected to a sixth wiring,
wherein one of a source and a drain of the seventh transistor is electrically connected to the fifth wiring,
wherein the other of the source and the drain of the seventh transistor is electrically connected to the third wiring,
wherein a gate of the seventh transistor is electrically connected to a seventh wiring,
wherein one of a source and a drain of the eighth transistor is electrically connected to a gate of the sixth transistor,
wherein a gate of the eighth transistor is electrically connected to the first wiring,
wherein one of a source and a drain of the ninth transistor is electrically connected to the gate of the sixth transistor,
wherein the other of the source and the drain of the ninth transistor is electrically connected to the third wiring, and
wherein a gate of the ninth transistor is electrically connected to the seventh wiring.
2. The semiconductor device according to claim 1 ,
wherein the fourth transistor is configured to control a potential of the gate of the first transistor, and
wherein the eighth transistor is configured to control a potential of the gate of the sixth transistor.
3. The semiconductor device according to claim 1 ,
wherein the first wiring is configured to output a first output signal,
wherein the second wiring is configured to be supplied with a first clock signal,
wherein the third wiring is configured to be supplied with a ground potential,
wherein the fourth wiring is configured to be supplied with a first signal,
wherein the fifth wiring is configured to output a second output signal,
wherein the sixth wiring is configured to be supplied with a second clock signal, and
wherein the seventh wiring is configured to be supplied with a second signal.
4. The semiconductor device according to claim 1 ,
wherein a ratio of a channel width of the fourth transistor to a channel length of the fourth transistor is larger than a ratio of a channel width of the ninth transistor to a channel length of the ninth transistor.
5. The semiconductor device according to claim 1 ,
wherein the other of the source and the drain of the third transistor is directly connected to the fourth wiring, and
wherein the gate of the third transistor is directly connected to the fourth wiring.
6. A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to a third wiring,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to a fourth wiring,
wherein a gate of the third transistor is electrically connected to the fourth wiring,
wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the first transistor,
wherein a gate of the fourth transistor is electrically connected to a fifth wiring,
wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the second transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the third wiring,
wherein a gate of the fifth transistor is electrically connected to the gate of the first transistor,
wherein one of a source and a drain of the sixth transistor is electrically connected to the fifth wiring,
wherein the other of the source and the drain of the sixth transistor is electrically connected to a sixth wiring,
wherein one of a source and a drain of the seventh transistor is electrically connected to the fifth wiring,
wherein the other of the source and the drain of the seventh transistor is electrically connected to the third wiring, wherein a gate of the seventh transistor is electrically connected to a seventh wiring,
wherein one of a source and a drain of the eighth transistor is electrically connected to a gate of the sixth transistor,
wherein a gate of the eighth transistor is electrically connected to the first wiring,
wherein one of a source and a drain of the ninth transistor is electrically connected to the gate of the sixth transistor,
wherein the other of the source and the drain of the ninth transistor is electrically connected to the third wiring,
wherein a gate of the ninth transistor is electrically connected to the seventh wiring,
wherein the fourth transistor is configured to control a potential of the gate of the first transistor,
wherein the eighth transistor is configured to control a potential of the gate of the sixth transistor,
wherein the first wiring is configured to output a first output signal,
wherein the second wiring is configured to be supplied with a first clock signal,
wherein the third wiring is configured to be supplied with a ground potential,
wherein the fourth wiring is configured to be supplied with a first signal,
wherein the fifth wiring is configured to output a second output signal,
wherein the sixth wiring is configured to be supplied with a second clock signal,
wherein the seventh wiring is configured to be supplied with a second signal, and
wherein a ratio of a channel width of the fourth transistor to a channel length of the fourth transistor is larger than a ratio of a channel width of the ninth transistor to a channel length of the ninth transistor.
7. A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to a third wiring,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor,
wherein the other of the source and the drain of the third transistor is directly connected to a fourth wiring,
wherein a gate of the third transistor is directly connected to the fourth wiring,
wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the first transistor,
wherein a gate of the fourth transistor is electrically connected to a fifth wiring,
wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the second transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the third wiring,
wherein a gate of the fifth transistor is electrically connected to the gate of the first transistor,
wherein one of a source and a drain of the sixth transistor is electrically connected to the fifth wiring,
wherein the other of the source and the drain of the sixth transistor is electrically connected to a sixth wiring,
wherein one of a source and a drain of the seventh transistor is electrically connected to the fifth wiring,
wherein the other of the source and the drain of the seventh transistor is electrically connected to the third wiring,
wherein a gate of the seventh transistor is electrically connected to a seventh wiring,
wherein one of a source and a drain of the eighth transistor is electrically connected to a gate of the sixth transistor,
wherein a gate of the eighth transistor is electrically connected to the first wiring,
wherein one of a source and a drain of the ninth transistor is electrically connected to the gate of the sixth transistor,
wherein the other of the source and the drain of the ninth transistor is electrically connected to the third wiring,
wherein a gate of the ninth transistor is electrically connected to the seventh wiring,
wherein the fourth transistor is configured to control a potential of the gate of the first transistor,
wherein the eighth transistor is configured to control a potential of the gate of the sixth transistor,
wherein the first wiring is configured to output a first output signal,
wherein the second wiring is configured to be supplied with a first clock signal,
wherein the third wiring is configured to be supplied with a ground potential,
wherein the fourth wiring is configured to be supplied with a first signal,
wherein the fifth wiring is configured to output a second output signal,
wherein the sixth wiring is configured to be supplied with a second clock signal,
wherein the seventh wiring is configured to be supplied with a second signal, and
wherein a ratio of a channel width of the fourth transistor to a channel length of the fourth transistor is larger than a ratio of a channel width of the ninth transistor to a channel length of the ninth transistor.