Methods of forming a semiconductor device

1. A method of forming a semiconductor device, comprising:

providing a semiconductor substrate;

forming a first isolation structure and a second isolation structure for defining a first region and a second region in the semiconductor substrate;

performing a recessing process, such that the semiconductor substrate and the second isolation structure in the second region are recessed;

forming a first gate structure on the substrate in the first region, and a second gate structure on the substrate in the second region;

forming a first source/drain (S/D) region in the substrate within the first region and beside the first gate structure, and a second S/D region in the substrate within the second region and beside the second gate structure, wherein the first isolation structure is disposed laterally aside and in contact with the first S/D region within the first region, and the second isolation structure is disposed laterally aside and in contact with the second S/D region within the second region, wherein a top surface of the second isolation structure in the second region is lower than a top surface of the first isolation structure in the first region; and

forming a first S/D contact connected to the first S/D region and a second S/D contact connected to the second S/D region, wherein the first S/D contact and the second S/D contact are formed separately.

2. The method of claim 1 , wherein the first S/D contact is formed after forming the second S/D contact, and forming the second S/D contact and the first S/D contact comprises:

forming an interlayer dielectric layer to cover the first gate structure and the second gate structure;

patterning the interlayer dielectric layer using a first mask layer as a mask to define a second contact hole in the interlayer dielectric layer;

forming the second S/D contact in the second contact hole connected to the second S/D region;

removing the first patterned mask layer;

patterning the interlayer dielectric using a second mask layer as a mask to define a first contact hole in the interlayer dielectric layer;

forming the first contact in the first contact hole connected to the first S/D region; and

removing the second mask layer.

3. The method of claim 2 , wherein the second mask layer is formed with a second opening for defining the second contact hole, the first mask layer is formed with a first opening for defining the first contact hole, and a width of the second opening is larger than a width of the first opening.

4. The method of claim 1 , further comprising:

forming a first gate contact connected to a first gate electrode of the first gate structure; and

forming a second gate contact connected to a second gate electrode of the second gate structure.

5. The method of claim 4 , wherein the first S/D contact, the first gate contact and the second gate contact are simultaneously formed after forming the second S/D contact.

6. The method of claim 1 , wherein a height of the second S/D contact is larger than a height of the first S/D contact.

7. The method of claim 1 , wherein a bottom width of the second S/D contact is larger than a bottom width of the first S/D contact.

8. A method of forming a semiconductor device, comprising:

providing a semiconductor substrate;

forming a first isolation structure and a second isolation structure for defining a first region and a second region in the semiconductor substrate;

performing a recessing process, such that the semiconductor substrate and the second isolation structure in the second region are recessed;

forming a first gate structure on the substrate in the first region, and a second gate structure on the substrate in the second region;

forming a first source/drain (S/D) region in the substrate within the first region and beside the first gate structure, and a second S/D region in the substrate within the second region and beside the second gate structure, wherein the first S/D region has a first silicide layer formed thereon, and the second S/D region has a second silicide layer formed thereon, and a top surface of the second isolation structure in the second region is substantially coplanar with a top surface of the second silicide layer; and

forming a first S/D contact connected to the first S/D region and a second S/D contact connected to the second S/D region, wherein the first S/D contact and the second S/D contact are formed separately.

9. The method of claim 1 , wherein the first S/D contact is formed after forming the second S/D contact, and forming the second S/D contact and the first S/D contact comprises:

forming an interlayer dielectric layer to cover the first gate structure and the second gate structure;

patterning the interlayer dielectric layer using a first mask layer as a mask to define a second contact hole in the interlayer dielectric layer;

forming the second S/D contact in the second contact hole connected to the second S/D region;

removing the first patterned mask layer;

patterning the interlayer dielectric using a second mask layer as a mask to define a first contact hole in the interlayer dielectric layer;

forming the first contact in the first contact hole connected to the first S/D region; and

removing the second mask layer.

10. The method of claim 9 , wherein the second mask layer is formed with a second opening for defining the second contact hole, the first mask layer is formed with a first opening for defining the first contact hole, and a width of the second opening is larger than a width of the first opening.

11. The method of claim 8 , further comprising:

forming a first gate contact connected to a first gate electrode of the first gate structure; and

forming a second gate contact connected to a second gate electrode of the second gate structure.

12. The method of claim 11 , wherein the first S/D contact, the first gate contact and the second gate contact are simultaneously formed after forming the second S/D contact.

13. The method of claim 8 , wherein a height of the second S/D contact is larger than a height of the first S/D contact, and a bottom width of the second S/D contact is larger than a bottom width of the first S/D contact.

14. The method of claim 8 , wherein the top surface of the second isolation structure in the second region is lower than a top surface of the first isolation structure in the first region.

15. A method of forming a semiconductor device, comprising:

providing a semiconductor substrate;

forming a first isolation structure and a second isolation structure for defining a first region and a second region in the semiconductor substrate;

performing a recessing process to remove a portion of the semiconductor substrate and a portion of the second isolation structure;

forming a first gate structure on the substrate in the first region, and a second gate structure on the substrate in the second region;

forming a first source/drain (S/D) region in the substrate within the first region and beside the first gate structure, and a second S/D region in the substrate within the second region and beside the second gate structure, wherein the first S/D region has a first silicide layer formed thereon, and the second S/D region has a second silicide layer formed thereon, wherein the first isolation structure is disposed laterally aside and in contact with the first S/D region within the first region, and the second isolation structure is disposed laterally aside and in contact with the second S/D region within the second region, wherein a top surface of the second isolation structure in the second region is lower than a top surface of the first isolation structure in the first region; and

forming a first S/D contact connected to the first S/D region and landing on the first silicide layer and a second S/D contact connected to the second S/D region and landing on the second silicide layer, wherein the first S/D contact and the second S/D contact are formed separately,

wherein a contact area between the second silicide layer of the second S/D region and the second S/D contact is larger than a contact area between the first silicide layer of the first S/D region and the first S/D contact.

16. The method of claim 15 , wherein the first S/D contact is formed after forming the second S/D contact, and forming the second S/D contact and the first S/D contact comprises:

forming an interlayer dielectric layer to cover the first gate structure and the second gate structure;

patterning the interlayer dielectric layer using a first mask layer as a mask to define a second contact hole in the interlayer dielectric layer;

forming the second S/D contact in the second contact hole connected to the second S/D region;

removing the first patterned mask layer;

patterning the interlayer dielectric using a second mask layer as a mask to define a first contact hole in the interlayer dielectric layer;

forming the first contact in the first contact hole connected to the first S/D region; and

removing the second mask layer.

17. The method of claim 16 , wherein the second mask layer is formed with a second opening for defining the second contact hole, the first mask layer is formed with a first opening for defining the first contact hole, and a width of the second opening is larger than a width of the first opening.

18. The method of claim 15 , further comprising:

forming a first gate contact connected to a first gate electrode of the first gate structure; and

forming a second gate contact connected to a second gate electrode of the second gate structure.

19. The method of claim 18 , wherein the first S/D contact, the first gate contact and the second gate contact are simultaneously formed after forming the second S/D contact.

20. The method of claim 15 , wherein a height of the second S/D contact is larger than a height of the first S/D contact, and a bottom width of the second S/D contact is larger than a bottom width of the first S/D contact.