IP Library › Granted Patent US 11,894,474
Granted Patent B2
US 11,894,474 · App. 16/562,889 · Granted Feb 6, 2024

Silicon photonic integrated lens compatible with wafer processing

Inventors: Priyanka Dobriyal (Milpitas, CA); Ankur Agrawal (Chandler, AZ); Susheel Jadhav (Chandler, AZ); Quan Tran (Fremont, CA); Raghuram Narayan (Newark, CA); Raiyomand Aspandiar (Portland, OR); Kenneth Brown (Tempe, AZ); John Heck (Berkeley, CA)
Assignee: Intel Corporation
H01L31/02327G02B1/11G02B3/0012G02B3/0056G02B6/428H01L23/5385H01L25/167H01L31/02005H01L31/02019H01L31/02161H01L31/1876G02B6/241
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,894,474
App. No.
16/562,889
Granted
Feb 6, 2024
Kind
B2
Abstract

Embodiments disclosed herein include optoelectronic systems and methods of forming such systems. In an embodiment the optoelectronic system comprises a board, and a carrier attached to the board. In an embodiment, a first die is on the carrier. In an embodiment, the first die is a photonics die, and a surface of the first die is covered by an optically transparent layer.

Claims (18)

1. A semiconductor die, comprising:

a semiconductor substrate having a first surface and a second surface;

a first lens and a second lens over the first surface, the second lens laterally spaced apart from the first lens; and

an optically transparent layer over the first lens and the second lens, wherein a first surface of the optically transparent layer is conformal to a surface of the first lens and the second lens and to the first surface of the semiconductor substrate, and wherein a second surface of the optically transparent layer is substantially flat over the first lens and the second lens and between the first lens and the second lens, the second surface opposite the first surface.

2. The semiconductor die of claim 1 , wherein the optically transparent layer is over the entire first surface.

3. The semiconductor die of claim 1 , wherein a maximum thickness of the optically transparent layer is approximately 100 μm or less.

4. The semiconductor die of claim 3 , wherein the maximum thickness of the optically transparent layer is approximately 20 μm or less.

5. The semiconductor die of claim 1 , wherein the optically transparent layer comprises a polymer.

6. The semiconductor die of claim 5 , wherein the optically transparent layer comprises poly (para-xylylene) or structural analogs thereof.

7. The semiconductor die of claim 1 , further comprising:

an antireflective coating over the optically transparent layer.

8. The semiconductor die of claim 1 , wherein the first lens and the second lens are part of the semiconductor substrate.

9. The semiconductor die of claim 1 , wherein the semiconductor substrate is a silicon substrate.

10. The semiconductor die of claim 1 , wherein the semiconductor die is a photonics die.

11. A semiconductor die, comprising:

a semiconductor substrate having a first surface and a second surface;

a lens over the first surface; and

an optically transparent layer over the lens, wherein the optically transparent layer comprises a polymer comprising poly (para-xylylene) or structural analogs thereof.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 4, 2019
From: DOBRIYAL, PRIYANKA; AGRAWAL, ANKUR; JADHAV, SUSHEEL; TRAN, QUAN; NARAYAN, RAGHURAM; ASPANDIAR, RAIYOMAND; BROWN, KENNETH; HECK, JOHN
To: INTEL CORPORATION
Reel/Frame 050917/0256 →
Continuity (1)
Related Publication 20210074866A1 · Mar 11, 2021
Cited By (4)
US 12,253,723 US 12,442,990 US 12,591,096 US 12,724,212