IP Library › Granted Patent US 11,899,242
Granted Patent B2
US 11,899,242 · App. 17/075,014 · Granted Feb 13, 2024

Method of manufacturing a packaged device with optical pathway

Inventors: Hsien-Wei Chen (Hsinchu, TW); Ming-Fa Chen (Taichung, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
G02B6/13G02B6/124H01L21/56H01L23/528H01L24/08H01L24/32H01L24/83G02B2006/12107H01L23/481H01L2224/08145H01L2224/32145H01L2224/80895H01L2224/83896
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Quick Facts
Patent No.
US 11,899,242
App. No.
17/075,014
Granted
Feb 13, 2024
Kind
B2
Abstract

A packaged device includes an optical IC having an optical feature therein. An interconnect structure including layers of conductive features embedded within respective layers of dielectric materials overlie the optical feature. The interconnect structure is patterned to remove the interconnect structure from over the optical feature and a dielectric material having optically neutral properties, relative to a desired light wavelength(s) is formed over the optical feature. One or more electronic ICs may be bonded to the optical IC to form an integrated package.

Claims (46)

1. A method comprising;

forming an optical feature on a first integrated circuit die;

forming an interconnect structure overlying the first integrated circuit die, the interconnect structure including a plurality of stacked materials, wherein the interconnect structure imposes a first degree of optical interference on a light path extending to the optical feature;

removing a portion of the interconnect structure to thereby form a gap in the interconnect structure overlying the optical feature; and

filling the gap with a first bonding dielectric layer, the first bonding dielectric layer imposing a second degree of optical interference on the light path that is less than the first degree of optical interference, and

fusion bonding the first bonding dielectric layer to a second bonding dielectric layer, the second bonding dielectric layer being a topmost layer of a second integrated circuit die.

2. The method of claim 1 , further comprising:

depositing a protective dielectric material over the first bonding dielectric layer, wherein the protective dielectric material encapsulates the second integrated circuit die.

3. The method of claim 2 , further comprising forming conductive contact pads in an upper surface of the first bonding dielectric layer.

4. The method of claim 2 , wherein the first bonding dielectric layer and the protective dielectric material are formed of a same material composition.

5. The method of claim 1 , wherein:

the second integrated circuit die is an electronic.

6. The method of claim 3 , wherein the step of bonding a second integrated circuit die to the first integrated circuit die further includes forming a metallic bond between first bond pads embedded in the top surface of the first bonding dielectric layer and second bond pads embedded in a top surface of the second bonding dielectric layer.

7. The method of claim 2 , wherein an interface between the first bonding dielectric layer and the protective dielectric material is free of an optical interface.

8. The method of claim 1 , wherein the step of filling the gap with a first bonding dielectric layer comprises depositing a material selected from the group consisting of silicon oxide, silicon oxynitride, and silicon nitride.

9. A method comprising:

forming an optical feature on a first integrated circuit die;

forming an interconnect structure overlying the first integrated circuit die, the interconnect structure including a plurality of stacked dielectric layers wherein optical interfaces exist between respective ones of the stacked dielectric layers;

forming a gap in the interconnect structure by removing a portion of the interconnect structure overlying the optical feature; and

filling the gap and covering the interconnect structure with a first bonding dielectric layer;

fusion bonding a second integrated circuit die to the first bonding dielectric layer; and

forming a protective layer over the first bonding dielectric layer and encapsulating the second integrated circuit die, wherein the protective layer and the first bonding dielectric layer form an optical path over the optical feature.

10. The method of claim 9 , wherein the optical path has no optical interfaces to a height, from the optical feature, at least as high as the topmost surface of the interconnect structure.

11. The method of claim 10 , further comprising:

depositing a second bonding dielectric layer on the second integrated circuit die;

forming first bond pads in the first bonding dielectric layer and second bond pads in the second bonding dielectric layer;

applying a surface treatment process to the first bonding dielectric layer, the second bonding dielectric layer, or both; and

bringing the first bonding dielectric layer and the second bonding dielectric layer into contact and bringing the first bond pads and the second bond pads into contact.

12. The method of claim 9 , further comprising:

thinning a back side of a substrate of the first integrated circuit die to expose through substrate vias (TSVs) extending there through; and

forming electrical connectors in electrical contact with the TSVs.

13. The method of claim 9 , wherein the step of forming a protective layer over the first bonding dielectric layer and encapsulating the second integrated circuit die comprises forming the protective layer to extend to a height substantially level with a topmost surface of the second integrated die.

14. The method of claim 13 , wherein the first bonding dielectric layer and the protective layer comprises the same material.

15. The method of claim 11 , wherein a top of the protective layer is level with a top of the second integrated circuit die.

16. The method of claim 15 , wherein the protective layer has optical properties that are substantially the same as optical properties of the first bonding dielectric layer at pre-selected wavelengths.

17. The method of claim 9 , wherein the first bonding dielectric layer and the protective layer are formed using a same deposition process.

18. A method comprising:

forming an optical integrated circuit including

a through substrate via (TSV) extending through a back side of a silicon on insulator substrate;

an optical feature at a top side of the substrate, and,

an interconnect structure over the top side of the substrate, the interconnect structure providing electrical connection to electrical components of the optical integrated circuit;

removing a portion of the interconnect structure overlying the optical feature;

after removing the portion of the interconnect structure overlying the optical feature, depositing, over the optical feature, an optical path of dielectric material extending through the interconnect structure, the optical path of dielectric material being free of optical interfaces from a top surface of the dielectric material to a bottom surface to the interconnect structure, and

fusion bonding an electronic integrated circuit to a surface of the dielectric material forming the optical path of dielectric material.

19. The method of claim 18 , wherein the optical path of dielectric material includes a first dielectric layer to which a second integrated circuit is fusion bonded, and a second dielectric layer that encapsulates the second integrated circuit.

20. The method of claim 18 , the optical path of dielectric material is free of optical interfaces along its length from the optical feature to a topmost surface of the optical path of dielectric material.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 22, 2020
From: CHEN, HSIEN-WEI; CHEN, MING-FA
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 054144/0407 →
Continuity (2)
Provisional Application 63001207 · Mar 27, 2020
Related Publication 20210302654A1 · Sep 30, 2021