Driver circuit
A driver circuit which includes an output circuit and a control circuit coupled to the output circuit. The driver circuit includes a pull-up transistor with a silicon semiconductor layer. The control circuit includes a first transistor with an oxide semiconductor layer.
1. A driver circuit, comprising:
an output circuit comprising a pull-up transistor; and
a control circuit coupled to the output circuit, the control circuit comprising a first transistor;
wherein the pull-up transistor has a first control node, and the pull-up transistor is coupled to a first clock signal and a gate line;
wherein the output circuit further comprises an auxiliary transistor coupled to the pull-up transistor and a low voltage, and the auxiliary transistor has a second control node;
wherein the control circuit further comprises a second transistor, a third transistor, a fourth transistor, and a fifth transistor;
wherein a third end of the auxiliary transistor is directly connected to the second transistor, the third transistor, and the fourth transistor;
wherein the first transistor is coupled to a high voltage;
wherein the second transistor is coupled to the low voltage, the first control node, the first transistor, and the fifth transistor;
wherein the third transistor has a first end directly connected to the high voltage, a second end directly connected to the second control node, and a third end directly connected to a second clock signal; and
wherein the fourth transistor is coupled to the low voltage, the first transistor, the fifth transistor, and the auxiliary transistor;
wherein the second transistor has a bottom gate structure, and the auxiliary transistor has a top gate structure.
2. The driver circuit of claim 1 , wherein the second transistor and the auxiliary transistor commonly share a gate.
3. The driver circuit of claim 1 , wherein the second transistor and the auxiliary transistor form a stack-up structure.
4. The driver circuit of claim 1 , wherein the fifth transistor is coupled to the first control node and the first transistor, and a gate of the fifth transistor is directly connected to the high voltage.
5. The driver circuit of claim 1 , wherein the pull-up transistor has a first end coupled to the first clock signal, a second end coupled to the gate line and one end of a capacitor, and a third end coupled to the fifth transistor.
6. The driver circuit of claim 1 , wherein the pull-up transistor is a polysilicon transistor.
7. The driver circuit of claim 1 , wherein the first transistor has a first end directly connected to the high voltage, a second end coupled to the first control node, and a third end coupled to a previous gate line.
8. The driver circuit of claim 1 , wherein the first transistor is an oxide semiconductor transistor.
9. The driver circuit of claim 1 , wherein the second transistor has a first end coupled to the first control node, a second end coupled to the low voltage, and a third end coupled to the second control node.
10. The driver circuit of claim 1 , wherein the second transistor is an oxide semiconductor transistor.
11. The driver circuit of claim 1 , wherein the third transistor is an oxide semiconductor transistor.
12. The driver circuit of claim 1 , wherein the fourth transistor has a first end coupled to the second control node, a second end coupled to the low voltage, and a third end coupled to the first control node.
13. The driver circuit of claim 1 , wherein the fourth transistor is an oxide semiconductor transistor.