Voltage kick for improved erase efficiency in a memory device
The memory device includes a plurality of memory cell that arranged in an array, which includes a plurality of channels that are in electrical communication with a source line. The memory device also includes a controller that is configured to erase the memory cells in at least one erase pulse. During the at least one erase pulse, the controller is configured to drive the source line to an elevated voltage that is equal to an erase voltage Vera plus a kick voltage V_kick for a duration t_kick. The controller is then configured to reduce the voltage of the source line to the erase voltage Vera such that a voltage of the channel remains elevated during the entire erase pulse, including after the voltage of the source line has been reduced to the erase voltage Vera.
1. A method of operating a memory device, comprising the steps of:
preparing a memory device that includes a plurality of memory cells arranged in an array that includes a plurality of channels that are in electrical communication with a source line; and
in an erase pulse, driving the source line to an elevated voltage that is equal to an erase voltage Vera plus a kick voltage V_kick for a duration t_kick and then reducing the voltage of the source line to the erase voltage Vera to increase channel potential during the entire erase pulse,
wherein the kick voltage V_kick is in the range of 2 and 3 V and the duration t_kick is in the range of 1 and 10 μs.
2. The method as set forth in claim 1 wherein the memory device has a CMOS under array architecture with the source line being located under the array of memory cells.
3. The method as set forth in claim 2 wherein after the source line is reduced to the erase voltage Vera, the source line is held at a constant Vera for the remainder of the erase pulse.
4. The method as set forth in claim 2 , wherein the erase pulse where the source line is driven to the elevated voltage is a first erase pulse or a second erase pulse of a two pulse erase operation.
5. A memory device, comprising:
a plurality of memory cells arranged in an array that includes a plurality of channels that are in electrical communication with a source line; and
a controller configured to erase the memory cells in at least one erase pulse, during the at least one erase pulse, the controller being configured to
drive the source line to an elevated voltage that is equal to an erase voltage Vera plus a kick voltage V_kick for a duration t_kick, and then
reduce the voltage of the source line to the erase voltage Vera such that a voltage of the channel remains elevated during the entire erase pulse,
wherein the kick voltage V_kick is in the range of 2 and 3 V and the duration t_kick is in the range of 1 and 10 μs.
6. The memory device as set forth in claim 5 wherein the source line is located under the array of memory cells and the memory device has a CMOS under array architecture.
7. The memory device as set forth in claim 6 wherein after the controller reduces the source line to the erase voltage Vera, the source line is held at a constant Vera for the remainder of the erase pulse.
8. The method as set forth in claim 6 , wherein the erase pulse where the controller drives the source line to the elevated voltage is a first erase pulse or a second erase pulse of a two pulse erase operation.
9. An apparatus, comprising:
a plurality of memory cells arranged in an array that includes a plurality of channels that are in electrical communication with a source line; and
an erasing means for erasing the memory cells in at least one erase pulse, during the at least one erase pulse, the erasing means being configured to
drive the source line to an elevated voltage that is equal to an erase voltage Vera plus a kick voltage V_kick for a duration t_kick, and then
reduce the voltage of the source line to the erase voltage Vera such that a voltage of the channel remains elevated during the entire erase pulse,
wherein the kick voltage V_kick is in the range of 2 and 3 V and the duration t_kick is in the range of 1 and 10 μs.
10. The apparatus as set forth in claim 9 wherein the source line is located under the array of memory cells and the memory device has a CMOS under array architecture.