SiC MOSFET with transverse P+ region
A silicon carbide MOSFET device that includes a silicon carbide substrate of a first dopant type; a first silicon carbide layer of the first dopant type on top of the silicon carbide substrate; a second silicon carbide layer of a second dopant type embedded in a top portion of the first silicon carbide layer; a third silicon carbide layer of the first dopant type embedded in a top portion of the second silicon carbide layer; a gate oxide layer overlapped to the first silicon carbide layer, the second silicon carbide layer and the third silicon carbide layer; and a fourth silicon carbide layer at least partially overlapping with the second silicon carbide layer along a direction normal to the silicon carbide substrate. The first silicon carbide layer has lower doping than the silicon carbide substrate and defines a drift region. The third silicon carbide layer has higher doping than the first silicon carbide layer. The third silicon carbide layer includes a plurality of third portions that run substantially along a first direction. The second silicon carbide layer includes a plurality of second portions that run substantially along the first direction. The fourth silicon carbide layer includes a plurality of fourth portions that run substantially along a second direction perpendicular to the first direction. The first and second directions each is parallel to the silicon carbide substrate. The transversely arranged P+ regions to N+ regions in some embodiments allow adequate P+ area to achieve good body diode performance and protection to the gate oxide, but without consuming significant area of the MOSFET cell.
1. A silicon carbide MOSFET device, comprising:
a) a silicon carbide substrate of a first dopant type;
b) a first silicon carbide layer of the first dopant type on top of the silicon carbide substrate, the first silicon carbide layer having lower doping than the silicon carbide substrate and defining a drift region;
c) a second silicon carbide layer of a second dopant type embedded in a top portion of the first silicon carbide layer; the second silicon carbide layer comprising a plurality of second portions that run substantially along a first direction;
d) a third silicon carbide layer of the first dopant type embedded in a top portion of the second silicon carbide layer; the third silicon carbide layer having higher doping than the first silicon carbide layer; the third silicon carbide layer comprising a plurality of third portions that run substantially along the first direction; and
e) a gate oxide layer overlapped to the first silicon carbide layer, the second silicon carbide layer and the third silicon carbide layer; and in touch with a polysilicon layer;
wherein, the device further comprises a fourth silicon carbide layer at least partially overlapping with the second silicon carbide layer along a direction normal to the silicon carbide substrate; the fourth silicon carbide layer, which has higher doping than the second silicon carbide layer, comprising a plurality of fourth portions that run substantially along a second direction perpendicular to the first direction; the first and second directions each being parallel to the silicon carbide substrate;
wherein the first dopant type is N and the second dopant type is P: the third silicon carbide layer being a N+ layer, and the third portions of the third silicon carbide layer being separated from each other along the second direction; the fourth silicon carbide layer being a P+ layer, and the fourth portions are P+ portions which are separated from each other along the first direction; and
wherein the second silicon carbide layer comprises a plurality of P-well regions separated from each other along the second direction.
2. The silicon carbide MOSFET device according to claim 1 , wherein a depth of the fourth silicon carbide layer is equal to or smaller than a depth of the second silicon carbide layer.
3. The silicon carbide MOSFET device according to claim 2 , wherein a spacing between the fourth portions of the fourth silicon carbide layer is equal to or smaller than a spacing of the P-well regions of the second silicon carbide layer.
4. The silicon carbide MOSFET device according to claim 1 , wherein a depth of the fourth silicon carbide layer is greater than a depth of the second silicon carbide layer.
5. The silicon carbide MOSFET device according to claim 4 , wherein a spacing between the fourth portions of the fourth silicon carbide layer is greater than a spacing of the P-well regions of the second silicon carbide layer.
6. The silicon carbide MOSFET device according to claim 1 , wherein the plurality of P-wells is doped using multiple consecutive ion implantations with gradually lower energy and lower dose.
7. The silicon carbide MOSFET device according to claim 1 , wherein the second silicon carbide layer comprises a P-base; the device further comprising a plurality of trenches.
8. The silicon carbide MOSFET device according to claim 7 , wherein a depth of the fourth silicon carbide layer is greater than a depth of the plurality of trenches.
9. The silicon carbide MOSFET device according to claim 7 , wherein the third silicon carbide layer comprises a P+ region sandwiched between two N+ regions on each of two opposite sides of the gate oxide layer.
10. The silicon carbide MOSFET device according to claim 7 , wherein the third silicon carbide layer comprises two N+ regions without P+ region on each of two opposite sides of the gate oxide layer.
11. The silicon carbide MOSFET device according to claim 7 , wherein the gate oxide layer comprises a plurality of oxide portions each formed along the sidewall direction in one of the plurality of trenches.
12. The silicon carbide MOSFET device according to claim 1 , wherein a width of the fourth silicon carbide layer along the first direction is a minimum width that a fabrication process of the device can achieve.
13. The silicon carbide MOSFET device according to claim 1 , wherein each of the fourth portions is in a strip, bamboo, I-beam or dumbbell shape when viewed from a direction perpendicular to the silicon carbide substrate.
14. The silicon carbide MOSFET device according to claim 1 , wherein the third silicon carbide layer comprises two N+ regions as the third portions which are disposed respectively on two opposite sides of the gate oxide layer.
15. The silicon carbide MOSFET device according to claim 1 , wherein the P+ portions are doped using multiple consecutive ion implantations with a double-peak profile.
16. A silicon carbide MOSFET device, comprising:
a) a silicon carbide substrate of a first dopant type;
b) a first silicon carbide layer of the first dopant type on top of the silicon carbide substrate, the first silicon carbide layer having lower doping than the silicon carbide substrate and defining a drift region;
c) a second silicon carbide layer of a second dopant type embedded in a top portion of the first silicon carbide layer; the second silicon carbide layer comprising a plurality of second portions that run substantially along a first direction;
d) a third silicon carbide layer of the first dopant type embedded in a top portion of the second silicon carbide layer; the third silicon carbide layer having higher doping than the first silicon carbide layer; the third silicon carbide layer comprising a plurality of third portions that run substantially along the first direction; and
e) a gate oxide layer overlapped to the first silicon carbide layer, the second silicon carbide layer and the third silicon carbide layer; and in touch with a polysilicon layer;
wherein, the device further comprises a fourth silicon carbide layer at least partially overlapping with the second silicon carbide layer along a direction normal to the silicon carbide substrate; the fourth silicon carbide layer, which has higher doping than the second silicon carbide layer, comprising a plurality of fourth portions that run substantially along a second direction perpendicular to the first direction; the first and second directions each being parallel to the silicon carbide substrate;
wherein the first dopant type is N and the second dopant type is P: the third silicon carbide layer being a N+ layer, and the third portions of the third silicon carbide layer being separated from each other along the second direction; the fourth silicon carbide layer being a P+ layer, and the fourth portions are P+ portions which are separated from each other along the first direction; and
wherein the third silicon carbide layer comprises two N+ regions as the third portions which are disposed respectively on two opposite sides of the gate oxide layer.
17. The silicon carbide MOSFET device according to claim 16 , wherein the second silicon carbide layer comprises a P-base; the device further comprising a plurality of trenches.
18. A silicon carbide MOSFET device, comprising:
a) a silicon carbide substrate of a first dopant type;
b) a first silicon carbide layer of the first dopant type on top of the silicon carbide substrate, the first silicon carbide layer having lower doping than the silicon carbide substrate and defining a drift region;
c) a second silicon carbide layer of a second dopant type embedded in a top portion of the first silicon carbide layer; the second silicon carbide layer comprising a plurality of second portions that run substantially along a first direction;
d) a third silicon carbide layer of the first dopant type embedded in a top portion of the second silicon carbide layer; the third silicon carbide layer having higher doping than the first silicon carbide layer; the third silicon carbide layer comprising a plurality of third portions that run substantially along the first direction; and
e) a gate oxide layer overlapped to the first silicon carbide layer, the second silicon carbide layer and the third silicon carbide layer; and in touch with a polysilicon layer;
wherein, the device further comprises a fourth silicon carbide layer at least partially overlapping with the second silicon carbide layer along a direction normal to the silicon carbide substrate; the fourth silicon carbide layer, which has higher doping than the second silicon carbide layer, comprising a plurality of fourth portions that run substantially along a second direction perpendicular to the first direction; the first and second directions each being parallel to the silicon carbide substrate;
wherein the first dopant type is N and the second dopant type is P: the third silicon carbide layer being a N+ layer, and the third portions of the third silicon carbide layer being separated from each other along the second direction; the fourth silicon carbide layer being a P+ layer, and the fourth portions are P+ portions which are separated from each other along the first direction; and
wherein the P+ portions are doped using multiple consecutive ion implantations with a double-peak profile.
19. A method of producing a silicon carbide MOSFET device, comprising the steps of:
a) providing a first silicon carbide layer of a first dopant type on top of a silicon carbide substrate; the first silicon carbide layer comprises first epitaxy layer and second epitaxy layer, which have same or different doping but both have lower doping than the silicon carbide substrate;
b) providing a second silicon carbide layer of a second dopant type embedded in a top portion of the first silicon carbide layer;
c) providing a third silicon carbide layer of the first dopant type embedded in a top portion of the second silicon carbide layer; the third silicon carbide layer having higher doping than the first silicon carbide layer; the third silicon carbide layer comprising a plurality of third portions that run substantially along a first direction;
d) providing a gate oxide layer overlapped to the first silicon carbide layer, the second silicon carbide layer and the third silicon carbide layer; and in touch with a polysilicon layer; and
e) providing a fourth silicon carbide layer at least partially overlapping with the second silicon carbide layer along a direction normal to the silicon carbide substrate; the fourth silicon carbide layer, which has higher doping than the second silicon carbide layer, comprises a plurality of fourth portions that run substantially along a second direction perpendicular to the first direction; the first and second directions each being parallel to the silicon carbide substrate;
wherein the first dopant type is N and the second dopant type is P: the third silicon carbide layer being a N+ layer, and the third portions of the third silicon carbide layer being separated from each other along the second direction; the fourth silicon carbide layer being a P+ layer, and the fourth portions are P+ portions which are separated from each other along the first direction; and
wherein the second silicon carbide layer comprises a plurality of P-well regions separated from each other along the second direction.
20. The method according to claim 19 , further comprises the steps of:
f) multiple consecutive ion implantations of first series of dopants on a first epitaxy layer to make the lower P+ portions;
g) multiple consecutive ion implantations of second series of dopants on a second epitaxy layer, which is deposited on top of the first epitaxy layer, to make the upper P+ portions;
wherein the second series of dopants join the first series of dopants along a depth direction of the fourth silicon carbide layer, and result in double-peak profile.