Method of making decoupling capacitor
View Patent ↗A method includes implanting a first dopant having a first dopant type into a substrate to define a plurality of source/drain (S/D) regions. The method further includes implanting a second dopant having the first dopant type into the substrate to define a channel region between adjacent S/D regions of the plurality of S/D regions, wherein a dopant concentration of the second dopant in the channel region is less than half of a dopant concentration of the first dopant in each of the plurality of S/D regions. The method further includes forming a gate stack over the channel region. The method further includes electrically coupling each of the plurality of S/D regions together.
1. A method comprising:
implanting a first dopant having a first dopant type into a substrate to define a plurality of source/drain (S/D) regions;
implanting a second dopant having the first dopant type into the substrate to define a channel region between adjacent S/D regions of the plurality of S/D regions, wherein a dopant concentration of the second dopant in the channel region is less than half of a dopant concentration of the first dopant in each of the plurality of S/D regions;
forming a gate stack over the channel region; and
electrically coupling each of the plurality of S/D regions together.
2. The method of claim 1 , further comprising implanting an n-well in the substrate.
3. The method of claim 2 , further comprising electrically coupling the n-well to each of the plurality of S/D regions.
4. A method comprising:
implanting a first dopant into a substrate to form a plurality of source/drain (S/D) regions in the substrate;
electrically coupling each of the plurality of S/D regions together;
implanting a second dopant into the substrate to define a channel region, wherein the channel region is between adjacent S/D regions of the plurality of S/D regions, wherein the second dopant and the first dopant are p-type, and a concentration of the second dopant in the channel region is less than a concentration of the first dopant in each of the plurality of S/D regions;
forming a gate stack over the channel region; and
forming an n-well in the substrate, wherein the n-well extends under the channel region and the adjacent S/D regions of the plurality of S/D regions.
5. The method of claim 4 , wherein implanting the second dopant comprises implanting the second dopant to a depth less than the implanting of the first dopant.
6. The method of claim 4 , further comprising electrically connecting the n-well with each of the plurality of S/D regions.
7. The method of claim 4 , further comprising electrically connecting the substrate to a reference voltage.
8. The method of claim 4 , further comprising implanting a third dopant to define a lightly doped drain (LDD) region below each of the plurality of S/D regions.
9. The method of claim 8 , wherein implanting the third dopant comprises defining the LDD region continuously extending below each of the plurality of S/D regions.
10. The method of claim 8 , wherein implanting the second dopant comprises defining the LDD region in contact with the channel region.
11. The method of claim 8 , wherein implanting the third dopant comprises implanting the third dopant after implanting the first dopant.
12. The method of claim 4 , wherein implanting the first dopant comprises implanting the first dopant after forming the n-well in the substrate.
13. A method comprising:
implanting a first dopant into a substrate to form a plurality of source/drain (S/D) regions in the substrate;
implanting a second dopant into the substrate to define a channel region, wherein the channel region is between adjacent S/D regions of the plurality of S/D regions, wherein the second dopant and the first dopant are p-type, and a concentration of the second dopant in the channel region is less than a concentration of the first dopant in each of the plurality of S/D regions;
implanting a third dopant into the substrate to define a lightly doped drain (LDD) region extending continuously under each of the plurality of S/D regions and under the channel region; and
forming a gate stack over the channel region.
14. The method of claim 13 , further comprising forming an n-well in the substrate, wherein the n-well extends under the channel region and the adjacent S/D regions of the plurality of S/D regions.
15. The method of claim 14 , further comprising electrically connecting each of the plurality of S/D regions to the n-well.
16. The method of claim 13 , wherein implanting the second dopant comprises implanting the second dopant to a depth equal to a depth of the first dopant.
17. The method of claim 13 , wherein implanting the third dopant comprises implanting the third dopant after implanting the second dopant.
18. The method of claim 13 , wherein forming the gate stack comprises:
forming a gate dielectric layer over the channel region; and
forming a gate electrode over the gate dielectric layer.
19. The method of claim 13 , further comprising forming a plurality of S/D contacts, wherein each of the plurality of S/D contact is formed over a corresponding S/D region of the plurality of S/D regions.
20. The method of claim 13 , wherein implanting the first dopants comprises implanting the first dopants prior to implanting the second dopants.