Memory with artificial intelligence mode
View Patent ↗Apparatuses and methods related to an artificial intelligence accelerator in memory are disclosed. An apparatus can include a number of registers configured to enable the apparatus to operate in an artificial intelligence mode to perform artificial intelligence operations and an artificial intelligence (AI) accelerator configured to perform the artificial intelligence operations using the data stored in the number of memory arrays. The AI accelerator can include hardware, software, and or firmware that is configured to perform operations associated with AI operations. The hardware can include circuitry configured as an adder and/or multiplier to perform operations, such as logic operations, associated with AI operations.
1. An apparatus, comprising:
a number of memory arrays;
a controller; and
a number of artificial intelligence (AI) registers, wherein the number of artificial intelligence registers are configured to enable artificial intelligence operations performed by the apparatus and wherein the number of AI registers are configured to be programmed to identify a status of the artificial intelligence operations.
2. The apparatus of claim 1 , wherein the number of artificial intelligence registers include a first number of registers that define a size of an input, a number of the input, and an initial and last address of the input.
3. The apparatus of claim 1 , wherein the number of artificial intelligence registers include a second number of registers that define a size of an output, a number of the input, and an initial and last address of the input.
4. The apparatus of claim 1 , wherein the number of artificial intelligence registers include a third number of registers that enable banks in the number of memory arrays for use during the artificial intelligence operations.
5. The apparatus of claim 1 , wherein the number of artificial intelligence registers include a fourth number of registers that define a size of a matrix in the neural network, an initial and last address of neurons in a neural network, a number of layers in the neural network.
6. The apparatus of claim 1 , wherein the number of artificial intelligence registers include a fifth number of registers that define a size of a first temporary block and an initial and last address of the first temporary block.
7. The apparatus of claim 1 , wherein the number of artificial intelligence registers include a sixth number of registers that define a size of a second temporary block and an initial and last address of the second temporary block.
8. The apparatus of claim 1 , wherein the number of artificial intelligence registers include a seventh number of registers that define a start and end address for activation functions and a resolution of the activation functions.
9. The apparatus of claim 1 , wherein the number of artificial intelligence registers include an eighth number of registers that define a size of a number of bias values, a start and end last address of the number of bias values, and the number of bias values.
10. An apparatus, comprising:
a number of memory arrays; and
a controller, coupled to the number of memory arrays, configured to:
enable an artificial intelligence mode for the memory device to perform artificial intelligence operations by writing an indicator in one of a number of registers; and
program the number of registers to identify a status of the artificial intelligence operations.
11. The apparatus of claim 10 , wherein the number of registers are programmed to indicate that the artificial intelligence operations are being performed.
12. The apparatus of claim 10 , wherein the number of registers are programmed to indicate that the artificial intelligence operations should be performed at full capability.
13. The apparatus of claim 10 , wherein the number of registers are programmed to indicate that only matrix calculations of the artificial intelligence operations should be performed.
14. The apparatus of claim 10 , wherein the number of registers are programmed to indicate that the artificial intelligence operations is to proceed to a next neuron and/or layer.
15. The apparatus of claim 10 , wherein the number of registers include a register that identifies a number of activations functions stored in the number of memory arrays used during the artificial intelligence operations.
16. The apparatus of claim 10 , wherein the controller is configured to perform, in response to enabling the artificial intelligence mode, the artificial intelligence operations using data stored in the number of memory arrays.
17. A method, comprising:
writing an indicator in one of a number of registers to enable an artificial intelligence mode for a memory device to perform artificial intelligence operations; and
programming the number of registers to identify a status of the artificial intelligence operations.
18. The method of claim 17 , further including programming the number of registers to indicate that the artificial intelligence operations are being performed.
19. The method of claim 17 , further including programming the number of registers to indicate that the artificial intelligence operations should be performed at full capability.
20. The method of claim 17 , further including programming the number of registers to indicate that only matrix calculations of the artificial intelligence operations should be performed.