IP Library Granted Patent US 11,923,282
Granted Patent B2
US 11,923,282 · App. 17/162,628 · Granted Mar 5, 2024

Wiring substrate

Inventor: Tetsuichiro Kasahara (Nagano, JP)
Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
H01L23/49822H01L21/486H01L23/49827H01L23/49838H01L21/4857H01L2224/48091
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Quick Facts
Patent No.
US 11,923,282
App. No.
17/162,628
Granted
Mar 5, 2024
Kind
B2
Abstract

A wiring substrate includes an insulation layer, a first wiring layer, and a second wiring layer. The first wiring layer is embedded in the insulation layer with an upper surface of the first wiring layer exposed from the insulation layer. The second wiring layer includes a terminal portion located at a lower position than a lower surface of the insulation layer and an embedded portion embedded in the insulation layer. The wiring substrate further includes a connection via connecting the first wiring layer and the embedded portion. The insulation layer includes an extension between the embedded portion and a lower surface of the first wiring layer. The extension includes a through hole. The connection via is located in the through hole of the extension.

Claims (20)

1. A wiring substrate comprising:

an insulation layer;

a first wiring layer embedded in the insulation layer with an upper surface of the first wiring layer exposed from the insulation layer;

a second wiring layer including:

a terminal portion located at a lower position than a lower surface of the insulation layer, and

an embedded portion embedded in the insulation layer; and

a connection via connecting the first wiring layer and the embedded portion of the second wiring layer,

wherein the insulation layer includes an extension between the embedded portion of the second wiring layer and a lower surface of the first wiring layer,

wherein the extension of the insulation layer includes a through hole extending through the extension in a thickness-wise direction,

wherein the first wiring layer includes a through hole extending through the first wiring layer in the thickness-wise direction at the same position as the through hole of the extension in a plan view,

wherein the connection via is integrally arranged in the through hole of the first wiring layer and the through hole of the insulation layer,

the connection via including:

a through portion located in the through hole of the first wiring layer; and

a connection portion located in the through hole of the insulation layer, and

wherein the through hole of the insulation layer has a diameter that is larger than a diameter of the through hole of the first wiring layer.

2. The wiring substrate according to claim 1 , wherein the upper surface of the first wiring layer and an upper surface of the insulation layer are located at the same height.

3. The wiring substrate according to claim 1 , wherein an upper surface of the connection via is located at a lower position than the upper surface of the first wiring layer.

4. A semiconductor device comprising:

the wiring substrate according to claim 1 ; and

at least one electronic component mounted on the wiring substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 29, 2021
From: KASAHARA, TETSUICHIRO
To: SHINKO ELECTRIC INDUSTRIES CO., LTD.
Reel/Frame 055082/0575 →
Priority Claims (1)
JP 2017-095240 · May 12, 2017 · national
Continuity (2)
Division 15964594 · Apr 27, 2018
Related Publication 20210151371A1 · May 20, 2021